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hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 

Instantiate a copy of the CPU_IDENTITY register block for each CPU
in an SSE-200.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-02-01 14:55:43 +00:00
parent 5aeb368966
commit ade67dcd4a
2 changed files with 31 additions and 0 deletions
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28
hw/arm/armsse.c
View File

@ -34,6 +34,7 @@ struct ARMSSEInfo {
bool has_ppus; bool has_ppus;
bool has_cachectrl; bool has_cachectrl;
bool has_cpusecctrl; bool has_cpusecctrl;
bool has_cpuid;
}; };
static const ARMSSEInfo armsse_variants[] = { static const ARMSSEInfo armsse_variants[] = {
@ -47,6 +48,7 @@ static const ARMSSEInfo armsse_variants[] = {
.has_ppus = false, .has_ppus = false,
.has_cachectrl = false, .has_cachectrl = false,
.has_cpusecctrl = false, .has_cpusecctrl = false,
.has_cpuid = false,
}, },
}; };
@ -314,6 +316,16 @@ static void armsse_init(Object *obj)
g_free(name); g_free(name);
} }
} }
if (info->has_cpuid) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cpuid%d", i);
sysbus_init_child_obj(obj, name, &s->cpuid[i],
sizeof(s->cpuid[i]),
TYPE_ARMSSE_CPUID);
g_free(name);
}
}
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
sizeof(s->nmi_orgate), TYPE_OR_IRQ, sizeof(s->nmi_orgate), TYPE_OR_IRQ,
&error_abort, NULL); &error_abort, NULL);
@ -864,6 +876,22 @@ static void armsse_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr);
} }
} }
if (info->has_cpuid) {
for (i = 0; i < info->num_cpus; i++) {
MemoryRegion *mr;
qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
object_property_set_bool(OBJECT(&s->cpuid[i]), true,
"realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr);
}
}
/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
/* Devices behind APB PPC1: /* Devices behind APB PPC1:

3
include/hw/arm/armsse.h
View File

@ -78,6 +78,7 @@
#include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysctl.h"
#include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/iotkit-sysinfo.h"
#include "hw/misc/armsse-cpuid.h"
#include "hw/misc/unimp.h" #include "hw/misc/unimp.h"
#include "hw/or-irq.h" #include "hw/or-irq.h"
#include "hw/core/split-irq.h" #include "hw/core/split-irq.h"
@ -153,6 +154,8 @@ typedef struct ARMSSE {
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
ARMSSECPUID cpuid[SSE_MAX_CPUS];
/* /*
* 'container' holds all devices seen by all CPUs. * 'container' holds all devices seen by all CPUs.
* 'cpu_container[i]' is the view that CPU i has: this has the * 'cpu_container[i]' is the view that CPU i has: this has the