From ad6aef5a665bec48153f300ca7ccd41423d5d7ff Mon Sep 17 00:00:00 2001
From: espes <espes@pequalsnp.com>
Date: Mon, 19 Oct 2015 18:24:45 +1100
Subject: [PATCH] nforce chipset seems to allow setting irq0-3 to level
 triggered

---
 hw/intc/i8259_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c
index 803d037f68..f1c84affa8 100644
--- a/hw/intc/i8259_common.c
+++ b/hw/intc/i8259_common.c
@@ -87,7 +87,7 @@ ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
     dev = DEVICE(isadev);
     qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
     qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
-    qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
+    // qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
     qdev_prop_set_bit(dev, "master", master);
     qdev_init_nofail(dev);