ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ppc/pnv: add a 'xscom_core_base' field to PnvChipClass 

The XSCOM addresses for the core registers are encoded in a slightly
different way on POWER8 and POWER9.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2016-11-14 10:12:55 +01:00 committed by David Gibson
parent 7bacfd7f72
commit ad521238b4
3 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/ppc/pnv.c
View File

@ -521,6 +521,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->cores_mask = POWER8E_CORE_MASK; k->cores_mask = POWER8E_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8; k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull; k->xscom_base = 0x003fc0000000000ull;
k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8E"; dc->desc = "PowerNV Chip POWER8E";
} }
@ -542,6 +543,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->cores_mask = POWER8_CORE_MASK; k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8; k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull; k->xscom_base = 0x003fc0000000000ull;
k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8"; dc->desc = "PowerNV Chip POWER8";
} }
@ -563,6 +565,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->cores_mask = POWER8_CORE_MASK; k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8; k->core_pir = pnv_chip_core_pir_p8;
k->xscom_base = 0x003fc0000000000ull; k->xscom_base = 0x003fc0000000000ull;
k->xscom_core_base = 0x10000000ull;
dc->desc = "PowerNV Chip POWER8NVL"; dc->desc = "PowerNV Chip POWER8NVL";
} }
@ -584,6 +587,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->cores_mask = POWER9_CORE_MASK; k->cores_mask = POWER9_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p9; k->core_pir = pnv_chip_core_pir_p9;
k->xscom_base = 0x00603fc00000000ull; k->xscom_base = 0x00603fc00000000ull;
k->xscom_core_base = 0x0ull;
dc->desc = "PowerNV Chip POWER9"; dc->desc = "PowerNV Chip POWER9";
} }
@ -691,7 +695,9 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
object_unref(OBJECT(pnv_core)); object_unref(OBJECT(pnv_core));
/* Each core has an XSCOM MMIO region */ /* Each core has an XSCOM MMIO region */
pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid), pnv_xscom_add_subregion(chip,
PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
core_hwid),
&PNV_CORE(pnv_core)->xscom_regs); &PNV_CORE(pnv_core)->xscom_regs);
i++; i++;
} }

1
include/hw/ppc/pnv.h
View File

@ -69,6 +69,7 @@ typedef struct PnvChipClass {
uint64_t cores_mask; uint64_t cores_mask;
hwaddr xscom_base; hwaddr xscom_base;
hwaddr xscom_core_base;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
} PnvChipClass; } PnvChipClass;

5
include/hw/ppc/pnv_xscom.h
View File

@ -40,7 +40,7 @@ typedef struct PnvXScomInterfaceClass {
} PnvXScomInterfaceClass; } PnvXScomInterfaceClass;
/* /*
* Layout of the XSCOM PCB addresses of EX core 1 * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
* *
* GPIO 0x1100xxxx * GPIO 0x1100xxxx
* SCOM 0x1101xxxx * SCOM 0x1101xxxx
@ -54,8 +54,7 @@ typedef struct PnvXScomInterfaceClass {
* PCB SLAVE 0x110Fxxxx * PCB SLAVE 0x110Fxxxx
*/ */
#define PNV_XSCOM_EX_BASE 0x10000000 #define PNV_XSCOM_EX_CORE_BASE(base, i) (base | (((uint64_t)i) << 24))
#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) << 24))
#define PNV_XSCOM_EX_CORE_SIZE 0x100000 #define PNV_XSCOM_EX_CORE_SIZE 0x100000
#define PNV_XSCOM_LPC_BASE 0xb0020 #define PNV_XSCOM_LPC_BASE 0xb0020