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target/arm: Enforce alignment for aa64 load-acq/store-rel 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-04-19 13:22:53 -07:00 committed by Peter Maydell
parent 4044a3cd1c
commit acb07e08d6
1 changed files with 14 additions and 9 deletions
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23
target/arm/translate-a64.c
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@ -2699,7 +2699,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
true, rn != 31, size); true, rn != 31, size);
do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, /* TODO: ARMv8.4-LSE SCTLR.nAA */
do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr); disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
return; return;
@ -2716,8 +2717,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
} }
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
false, rn != 31, size); false, rn != 31, size);
do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, /* TODO: ARMv8.4-LSE SCTLR.nAA */
disas_ldst_compute_iss_sf(size, false, 0), is_lasr); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, true,
rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
return; return;
@ -3505,15 +3507,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
int size = extract32(insn, 30, 2); int size = extract32(insn, 30, 2);
TCGv_i64 clean_addr, dirty_addr; TCGv_i64 clean_addr, dirty_addr;
bool is_store = false; bool is_store = false;
bool is_signed = false;
bool extend = false; bool extend = false;
bool iss_sf; bool iss_sf;
MemOp mop;
if (!dc_isar_feature(aa64_rcpc_8_4, s)) { if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
/* TODO: ARMv8.4-LSE SCTLR.nAA */
mop = size | MO_ALIGN;
switch (opc) { switch (opc) {
case 0: /* STLURB */ case 0: /* STLURB */
is_store = true; is_store = true;
@ -3525,21 +3530,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
is_signed = true; mop |= MO_SIGN;
break; break;
case 3: /* LDAPURS* 32-bit variant */ case 3: /* LDAPURS* 32-bit variant */
if (size > 1) { if (size > 1) {
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
is_signed = true; mop |= MO_SIGN;
extend = true; /* zero-extend 32->64 after signed load */ extend = true; /* zero-extend 32->64 after signed load */
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc);
if (rn == 31) { if (rn == 31) {
gen_check_sp_alignment(s); gen_check_sp_alignment(s);
@ -3552,13 +3557,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
if (is_store) { if (is_store) {
/* Store-Release semantics */ /* Store-Release semantics */
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, true);
} else { } else {
/* /*
* Load-AcquirePC semantics; we implement as the slightly more * Load-AcquirePC semantics; we implement as the slightly more
* restrictive Load-Acquire. * restrictive Load-Acquire.
*/ */
do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN, do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop,
extend, true, rt, iss_sf, true); extend, true, rt, iss_sf, true);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
} }