mirror of https://github.com/xemu-project/xemu.git
tests/tcg/xtensa: expand madd tests
Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -146,6 +146,110 @@ test madd_s
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FSR_I, FSR_I, FSR_I, FSR_I
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FSR_I, FSR_I, FSR_I, FSR_I
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test_end
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test_end
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test madd_s_precision
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test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \
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0x28800000, 0x28800000, 0x28800000, 0x28800000, \
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FSR__, FSR__, FSR__, FSR__
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test_end
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#if DFPU
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test madd_s_nan_dfpu
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/* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 = default NaN */
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
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F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + SNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* inf * 0 + QNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* madd/msub SNaN turns to QNaN and sets Invalid flag */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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#else
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test madd_s_nan_fpu2k
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/* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
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F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
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F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 = default NaN */
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test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
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F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 + SNaN1 = SNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
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F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* inf * 0 + QNaN1 = QNaN1 */
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
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F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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/* madd/msub SNaN is preserved */
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test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
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F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
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FSR__, FSR__, FSR__, FSR__
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test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
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F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \
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FSR__, FSR__, FSR__, FSR__
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test_end
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#endif
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test msub_s
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test msub_s
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test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
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test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
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0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
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0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
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