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target/hppa: Fix interruption based on default PSW 

The default PSW is set by the operating system with the PDC_PSW
firmware call.  Use that setting to decide if wide mode is to be
enabled for interruptions and EIRR usage.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Helge Deller 2023-10-17 11:36:37 +02:00 committed by Richard Henderson
parent 4e7abdb120
commit ab9af359c1
2 changed files with 16 additions and 4 deletions

2
target/hppa/cpu.h
View File

@ -137,6 +137,8 @@
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
#define CR_RC 0
#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */
#define PDC_PSW_WIDE_BIT 2
#define CR_PID1 8
#define CR_PID2 9
#define CR_PID3 12

18
target/hppa/int_helper.c
View File

@ -52,9 +52,17 @@ static void io_eir_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
HPPACPU *cpu = opaque;
int le_bit = ~data & 31;
CPUHPPAState *env = &cpu->env;
int widthm1 = 31;
int le_bit;
cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit;
/* The default PSW.W controls the width of EIRR. */
if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) {
widthm1 = 63;
}
le_bit = ~data & widthm1;
env->cr[CR_EIRR] |= 1ull << le_bit;
eval_interrupt(cpu);
}
@ -104,8 +112,10 @@ void hppa_cpu_do_interrupt(CPUState *cs)
/* step 1 */
env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
/* step 2 -- note PSW_W == 0 for !HPPA64. */
cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0));
/* step 2 -- Note PSW_W is masked out again for pa1.x */
cpu_hppa_put_psw(env,
(env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) |
(i == EXCP_HPMC ? PSW_M : 0));
/* step 3 */
env->cr[CR_IIASQ] = iasq_f >> 32;