From ab77fc611bf004dfd25ecad5b2c11261e32012e9 Mon Sep 17 00:00:00 2001 From: Dimitrije Nikolic Date: Mon, 20 Aug 2018 12:14:23 +0200 Subject: [PATCH] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is needed for implementing availability control of various instructions. Reviewed-by: "Aleksandar Markovic " Signed-off-by: "Aleksandar Markovic " --- target/mips/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4b1bb18316..10475a6c6b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1449,6 +1449,8 @@ typedef struct DisasContext { uint32_t opcode; int insn_flags; int32_t CP0_Config1; + int32_t CP0_Config3; + int32_t CP0_Config5; /* Routine used to access memory */ int mem_idx; TCGMemOp default_tcg_memop_mask; @@ -23307,6 +23309,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->saved_pc = -1; ctx->insn_flags = env->insn_flags; ctx->CP0_Config1 = env->CP0_Config1; + ctx->CP0_Config3 = env->CP0_Config3; + ctx->CP0_Config5 = env->CP0_Config5; ctx->btarget = 0; ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;