mirror of https://github.com/xemu-project/xemu.git
moved ACPI table init to BIOS - preliminary SMM support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2170 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
3b21e03e04
commit
ab1e34add6
494
hw/acpi.c
494
hw/acpi.c
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@ -19,13 +19,11 @@
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#include "vl.h"
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//#define DEBUG
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#define USE_SMM
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
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/* XXX: make them variable */
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#define PM_IO_BASE 0xb000
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#define SMI_CMD_IO_ADDR 0xb040
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct PIIX4PMState {
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@ -33,6 +31,8 @@ typedef struct PIIX4PMState {
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uint16_t pmsts;
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uint16_t pmen;
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uint16_t pmcntrl;
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uint8_t apmc;
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uint8_t apms;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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} PIIX4PMState;
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@ -46,10 +46,6 @@ typedef struct PIIX4PMState {
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#define SUS_EN (1 << 13)
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/* Note: only used for ACPI bios init. Could be deleted when ACPI init
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is integrated in Bochs BIOS */
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static PIIX4PMState *piix4_pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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uint32_t d;
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@ -195,22 +191,50 @@ static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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return val;
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}
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static void smi_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 1;
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#ifdef DEBUG
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printf("SMI cmd val=0x%02x\n", val);
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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switch(val) {
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case 0xf0: /* ACPI disable */
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s->pmcntrl &= ~SCI_EN;
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break;
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case 0xf1: /* ACPI enable */
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s->pmcntrl |= SCI_EN;
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break;
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if (addr == 0) {
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s->apmc = val;
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#ifdef USE_SMM
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
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#else
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/* emulation of what the SMM BIOS should do */
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switch(val) {
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case 0xf0: /* ACPI disable */
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s->pmcntrl &= ~SCI_EN;
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break;
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case 0xf1: /* ACPI enable */
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s->pmcntrl |= SCI_EN;
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break;
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}
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#endif
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} else {
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s->apms = val;
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}
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}
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 1;
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if (addr == 0) {
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val = s->apmc;
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} else {
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val = s->apms;
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}
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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#if defined(DEBUG)
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@ -218,17 +242,81 @@ static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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#endif
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}
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/* XXX: we still add it to the PIIX3 and we count on the fact that
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OSes are smart enough to accept this strange configuration */
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xfffe;
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/* XXX: need to improve memory and ioport allocation */
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#if defined(DEBUG)
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printf("PM: mapping to 0x%x\n", pm_io_base);
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#endif
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (address == 0x80)
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pm_io_space_update((PIIX4PMState *)d);
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}
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static void pm_save(QEMUFile* f,void *opaque)
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{
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PIIX4PMState *s = opaque;
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pci_device_save(&s->dev, f);
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qemu_put_be16s(f, &s->pmsts);
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qemu_put_be16s(f, &s->pmen);
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qemu_put_be16s(f, &s->pmcntrl);
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qemu_put_8s(f, &s->apmc);
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qemu_put_8s(f, &s->apms);
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qemu_put_timer(f, s->tmr_timer);
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qemu_put_be64s(f, &s->tmr_overflow_time);
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}
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static int pm_load(QEMUFile* f,void* opaque,int version_id)
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{
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PIIX4PMState *s = opaque;
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int ret;
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if (version_id > 1)
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return -EINVAL;
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
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qemu_get_be16s(f, &s->pmsts);
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qemu_get_be16s(f, &s->pmen);
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qemu_get_be16s(f, &s->pmcntrl);
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qemu_get_8s(f, &s->apmc);
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qemu_get_8s(f, &s->apms);
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qemu_get_timer(f, s->tmr_timer);
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qemu_get_be64s(f, &s->tmr_overflow_time);
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pm_io_space_update(s);
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return 0;
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}
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void piix4_pm_init(PCIBus *bus, int devfn)
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{
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PIIX4PMState *s;
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uint8_t *pci_conf;
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uint32_t pm_io_base;
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s = (PIIX4PMState *)pci_register_device(bus,
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"PM", sizeof(PIIX4PMState),
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devfn, NULL, NULL);
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devfn, NULL, pm_write_config);
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pci_conf = s->dev.config;
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pci_conf[0x00] = 0x86;
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pci_conf[0x01] = 0x80;
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@ -241,15 +329,11 @@ void piix4_pm_init(PCIBus *bus, int devfn)
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pci_conf[0x0e] = 0x00; // header_type
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pci_conf[0x3d] = 0x01; // interrupt pin 1
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pm_io_base = PM_IO_BASE;
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pci_conf[0x40] = pm_io_base | 1;
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pci_conf[0x41] = pm_io_base >> 8;
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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register_ioport_write(SMI_CMD_IO_ADDR, 1, 1, smi_cmd_writeb, s);
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register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
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register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
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/* XXX: which specification is used ? The i82731AB has different
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@ -260,356 +344,6 @@ void piix4_pm_init(PCIBus *bus, int devfn)
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(serial_hds[1] != NULL ? 0x90 : 0);
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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piix4_pm_state = s;
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}
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/* ACPI tables */
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/* XXX: move them in the Bochs BIOS ? */
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/*************************************************/
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/* Table structure from Linux kernel (the ACPI tables are under the
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BSD license) */
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#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
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uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
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uint32_t length; /* Length of table, in bytes, including header */\
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uint8_t revision; /* ACPI Specification minor version # */\
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uint8_t checksum; /* To make sum of entire table == 0 */\
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uint8_t oem_id [6]; /* OEM identification */\
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uint8_t oem_table_id [8]; /* OEM table identification */\
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uint32_t oem_revision; /* OEM revision number */\
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uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
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uint32_t asl_compiler_revision; /* ASL compiler revision number */
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struct acpi_table_header /* ACPI common table header */
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{
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ACPI_TABLE_HEADER_DEF
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};
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struct rsdp_descriptor /* Root System Descriptor Pointer */
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{
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uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
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uint8_t checksum; /* To make sum of struct == 0 */
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uint8_t oem_id [6]; /* OEM identification */
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uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
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uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
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uint32_t length; /* XSDT Length in bytes including hdr */
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uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
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uint8_t extended_checksum; /* Checksum of entire table */
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uint8_t reserved [3]; /* Reserved field must be 0 */
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};
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/*
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* ACPI 1.0 Root System Description Table (RSDT)
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*/
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struct rsdt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t table_offset_entry [2]; /* Array of pointers to other */
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/* ACPI tables */
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};
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/*
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* ACPI 1.0 Firmware ACPI Control Structure (FACS)
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*/
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struct facs_descriptor_rev1
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{
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uint8_t signature[4]; /* ACPI Signature */
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uint32_t length; /* Length of structure, in bytes */
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uint32_t hardware_signature; /* Hardware configuration signature */
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uint32_t firmware_waking_vector; /* ACPI OS waking vector */
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uint32_t global_lock; /* Global Lock */
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uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
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uint32_t reserved1 : 31; /* Must be 0 */
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uint8_t resverved3 [40]; /* Reserved - must be zero */
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};
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/*
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* ACPI 1.0 Fixed ACPI Description Table (FADT)
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*/
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struct fadt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t firmware_ctrl; /* Physical address of FACS */
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uint32_t dsdt; /* Physical address of DSDT */
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uint8_t model; /* System Interrupt Model */
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uint8_t reserved1; /* Reserved */
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uint16_t sci_int; /* System vector of SCI interrupt */
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uint32_t smi_cmd; /* Port address of SMI command port */
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uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
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uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
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uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
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uint8_t reserved2; /* Reserved - must be zero */
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uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
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uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
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uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
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uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
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uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
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uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
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uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
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uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
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uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
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uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
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uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
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uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
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uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
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uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
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uint8_t reserved3; /* Reserved */
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uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
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uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
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uint16_t flush_size; /* Size of area read to flush caches */
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uint16_t flush_stride; /* Stride used in flushing caches */
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uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
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uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
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uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
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uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
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uint8_t century; /* Index to century in RTC CMOS RAM */
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uint8_t reserved4; /* Reserved */
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uint8_t reserved4a; /* Reserved */
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uint8_t reserved4b; /* Reserved */
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#if 0
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uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
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uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
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uint32_t proc_c1 : 1; /* All processors support C1 state */
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uint32_t plvl2_up : 1; /* C2 state works on MP system */
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uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
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uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
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uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
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uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
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uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
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uint32_t reserved5 : 23; /* Reserved - must be zero */
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#else
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uint32_t flags;
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#endif
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};
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/*
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* MADT values and structures
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*/
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/* Values for MADT PCATCompat */
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#define DUAL_PIC 0
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#define MULTIPLE_APIC 1
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/* Master MADT */
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struct multiple_apic_table
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t local_apic_address; /* Physical address of local APIC */
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#if 0
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uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
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uint32_t reserved1 : 31;
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#else
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uint32_t flags;
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#endif
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};
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/* Values for Type in APIC_HEADER_DEF */
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#define APIC_PROCESSOR 0
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#define APIC_IO 1
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#define APIC_XRUPT_OVERRIDE 2
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#define APIC_NMI 3
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#define APIC_LOCAL_NMI 4
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#define APIC_ADDRESS_OVERRIDE 5
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#define APIC_IO_SAPIC 6
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#define APIC_LOCAL_SAPIC 7
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#define APIC_XRUPT_SOURCE 8
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#define APIC_RESERVED 9 /* 9 and greater are reserved */
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/*
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* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
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*/
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#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
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uint8_t type; \
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uint8_t length;
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/* Sub-structures for MADT */
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struct madt_processor_apic
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{
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APIC_HEADER_DEF
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uint8_t processor_id; /* ACPI processor id */
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uint8_t local_apic_id; /* Processor's local APIC id */
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#if 0
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uint32_t processor_enabled: 1; /* Processor is usable if set */
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uint32_t reserved2 : 31; /* Reserved, must be zero */
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#else
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uint32_t flags;
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#endif
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};
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struct madt_io_apic
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{
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APIC_HEADER_DEF
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uint8_t io_apic_id; /* I/O APIC ID */
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uint8_t reserved; /* Reserved - must be zero */
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uint32_t address; /* APIC physical address */
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uint32_t interrupt; /* Global system interrupt where INTI
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* lines start */
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};
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#include "acpi-dsdt.hex"
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static int acpi_checksum(const uint8_t *data, int len)
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{
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int sum, i;
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sum = 0;
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for(i = 0; i < len; i++)
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sum += data[i];
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return (-sum) & 0xff;
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}
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static void acpi_build_table_header(struct acpi_table_header *h,
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char *sig, int len)
|
||||
{
|
||||
memcpy(h->signature, sig, 4);
|
||||
h->length = cpu_to_le32(len);
|
||||
h->revision = 0;
|
||||
memcpy(h->oem_id, "QEMU ", 6);
|
||||
memcpy(h->oem_table_id, "QEMU", 4);
|
||||
memcpy(h->oem_table_id + 4, sig, 4);
|
||||
h->oem_revision = cpu_to_le32(1);
|
||||
memcpy(h->asl_compiler_id, "QEMU", 4);
|
||||
h->asl_compiler_revision = cpu_to_le32(1);
|
||||
h->checksum = acpi_checksum((void *)h, len);
|
||||
}
|
||||
|
||||
#define ACPI_TABLES_BASE 0x000e8000
|
||||
|
||||
/* base_addr must be a multiple of 4KB */
|
||||
void acpi_bios_init(void)
|
||||
{
|
||||
struct rsdp_descriptor *rsdp;
|
||||
struct rsdt_descriptor_rev1 *rsdt;
|
||||
struct fadt_descriptor_rev1 *fadt;
|
||||
struct facs_descriptor_rev1 *facs;
|
||||
struct multiple_apic_table *madt;
|
||||
uint8_t *dsdt;
|
||||
uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
|
||||
uint32_t pm_io_base, acpi_tables_size, madt_addr, madt_size;
|
||||
int i;
|
||||
|
||||
/* compute PCI I/O addresses */
|
||||
pm_io_base = (piix4_pm_state->dev.config[0x40] |
|
||||
(piix4_pm_state->dev.config[0x41] << 8)) & ~0x3f;
|
||||
|
||||
base_addr = ACPI_TABLES_BASE;
|
||||
|
||||
/* reserve memory space for tables */
|
||||
addr = base_addr;
|
||||
rsdp = (void *)(phys_ram_base + addr);
|
||||
addr += sizeof(*rsdp);
|
||||
|
||||
rsdt_addr = addr;
|
||||
rsdt = (void *)(phys_ram_base + addr);
|
||||
addr += sizeof(*rsdt);
|
||||
|
||||
fadt_addr = addr;
|
||||
fadt = (void *)(phys_ram_base + addr);
|
||||
addr += sizeof(*fadt);
|
||||
|
||||
/* XXX: FACS should be in RAM */
|
||||
addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
|
||||
facs_addr = addr;
|
||||
facs = (void *)(phys_ram_base + addr);
|
||||
addr += sizeof(*facs);
|
||||
|
||||
dsdt_addr = addr;
|
||||
dsdt = (void *)(phys_ram_base + addr);
|
||||
addr += sizeof(AmlCode);
|
||||
|
||||
addr = (addr + 7) & ~7;
|
||||
madt_addr = addr;
|
||||
madt_size = sizeof(*madt) +
|
||||
sizeof(struct madt_processor_apic) * smp_cpus +
|
||||
sizeof(struct madt_io_apic);
|
||||
madt = (void *)(phys_ram_base + addr);
|
||||
addr += madt_size;
|
||||
|
||||
acpi_tables_size = addr - base_addr;
|
||||
|
||||
cpu_register_physical_memory(base_addr, acpi_tables_size,
|
||||
base_addr | IO_MEM_ROM);
|
||||
|
||||
/* RSDP */
|
||||
memset(rsdp, 0, sizeof(*rsdp));
|
||||
memcpy(rsdp->signature, "RSD PTR ", 8);
|
||||
memcpy(rsdp->oem_id, "QEMU ", 6);
|
||||
rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
|
||||
rsdp->checksum = acpi_checksum((void *)rsdp, 20);
|
||||
|
||||
/* RSDT */
|
||||
rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
|
||||
rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
|
||||
acpi_build_table_header((struct acpi_table_header *)rsdt,
|
||||
"RSDT", sizeof(*rsdt));
|
||||
|
||||
/* FADT */
|
||||
memset(fadt, 0, sizeof(*fadt));
|
||||
fadt->firmware_ctrl = cpu_to_le32(facs_addr);
|
||||
fadt->dsdt = cpu_to_le32(dsdt_addr);
|
||||
fadt->model = 1;
|
||||
fadt->reserved1 = 0;
|
||||
fadt->sci_int = cpu_to_le16(piix4_pm_state->dev.config[0x3c]);
|
||||
fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
|
||||
fadt->acpi_enable = 0xf1;
|
||||
fadt->acpi_disable = 0xf0;
|
||||
fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
|
||||
fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
|
||||
fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->plvl2_lat = cpu_to_le16(50);
|
||||
fadt->plvl3_lat = cpu_to_le16(50);
|
||||
fadt->plvl3_lat = cpu_to_le16(50);
|
||||
/* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
|
||||
fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
|
||||
acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
|
||||
sizeof(*fadt));
|
||||
|
||||
/* FACS */
|
||||
memset(facs, 0, sizeof(*facs));
|
||||
memcpy(facs->signature, "FACS", 4);
|
||||
facs->length = cpu_to_le32(sizeof(*facs));
|
||||
|
||||
/* DSDT */
|
||||
memcpy(dsdt, AmlCode, sizeof(AmlCode));
|
||||
|
||||
/* MADT */
|
||||
{
|
||||
struct madt_processor_apic *apic;
|
||||
struct madt_io_apic *io_apic;
|
||||
|
||||
memset(madt, 0, madt_size);
|
||||
madt->local_apic_address = cpu_to_le32(0xfee00000);
|
||||
madt->flags = cpu_to_le32(1);
|
||||
apic = (void *)(madt + 1);
|
||||
for(i=0;i<smp_cpus;i++) {
|
||||
apic->type = APIC_PROCESSOR;
|
||||
apic->length = sizeof(*apic);
|
||||
apic->processor_id = i;
|
||||
apic->local_apic_id = i;
|
||||
apic->flags = cpu_to_le32(1);
|
||||
apic++;
|
||||
}
|
||||
io_apic = (void *)apic;
|
||||
io_apic->type = APIC_IO;
|
||||
io_apic->length = sizeof(*io_apic);
|
||||
io_apic->io_apic_id = smp_cpus;
|
||||
io_apic->address = cpu_to_le32(0xfec00000);
|
||||
io_apic->interrupt = cpu_to_le32(0);
|
||||
|
||||
acpi_build_table_header((struct acpi_table_header *)madt,
|
||||
"APIC", madt_size);
|
||||
}
|
||||
|
||||
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue