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target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]() 

When CPUArchState* is available (here CPUX86State*), we can
use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*).
The QOM cast X86_CPU() macro will be slower when building with
--enable-qom-cast-debug.

Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr
instead of a CPUState* to avoid an extra cast.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Roman Bolshakov <roman@roolebo.dev>
Tested-by: Roman Bolshakov <roman@roolebo.dev>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231009110239.66778-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-10-09 12:35:04 +02:00
parent 82b641d626
commit a9e445df54
3 changed files with 14 additions and 15 deletions
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4
target/i386/hvf/hvf.c
View File

@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu)
{
load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
simulate_rdmsr(cpu);
simulate_rdmsr(env);
} else {
simulate_wrmsr(cpu);
simulate_wrmsr(env);
}
env->eip += ins_len;
store_regs(cpu);

21
target/i386/hvf/x86_emu.c
View File

@ -663,11 +663,10 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void simulate_rdmsr(struct CPUState *cpu)
void simulate_rdmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
CPUState *cs = env_cpu(env);
X86CPU *x86_cpu = env_archcpu(env);
CPUState *cpu = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
@ -746,8 +745,8 @@ void simulate_rdmsr(struct CPUState *cpu)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_rdmsr(env_cpu(env));
simulate_rdmsr(env);
env->eip += decode->len;
}
void simulate_wrmsr(struct CPUState *cpu)
void simulate_wrmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *x86_cpu = env_archcpu(env);
CPUState *cpu = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@ -856,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu)
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_wrmsr(env_cpu(env));
simulate_wrmsr(env);
env->eip += decode->len;
}

4
target/i386/hvf/x86_emu.h
View File

@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
void simulate_rdmsr(struct CPUState *cpu);
void simulate_wrmsr(struct CPUState *cpu);
void simulate_rdmsr(CPUX86State *env);
void simulate_wrmsr(CPUX86State *env);
target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);