mirror of https://github.com/xemu-project/xemu.git
target/arm: Convert exception generation instructions to decodetree
Convert the exception generation instructions SVC, HVC, SMC, BRK and HLT to decodetree. The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and DCPS3 just in order to then make them UNDEF; as with DRPS, we don't bother to decode them, but document the patterns in a64.decode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
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Peter Maydell
parent
6e3c8049ad
commit
a97d3c18f6
target/arm/tcg
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@ -215,3 +215,18 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
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SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
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SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
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SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
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# Exception generation
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@i16 .... .... ... imm:16 ... .. &i
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SVC 1101 0100 000 ................ 000 01 @i16
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HVC 1101 0100 000 ................ 000 10 @i16
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SMC 1101 0100 000 ................ 000 11 @i16
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BRK 1101 0100 001 ................ 000 00 @i16
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HLT 1101 0100 010 ................ 000 00 @i16
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# These insns always UNDEF unless in halting debug state, which
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# we don't implement. So we don't need to decode them. The patterns
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# are listed here as documentation.
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# DCPS1 1101 0100 101 ................ 000 01 @i16
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# DCPS2 1101 0100 101 ................ 000 10 @i16
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# DCPS3 1101 0100 101 ................ 000 11 @i16
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@ -2313,119 +2313,77 @@ static bool trans_SYS(DisasContext *s, arg_SYS *a)
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return true;
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}
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/* Exception generation
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*
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* 31 24 23 21 20 5 4 2 1 0
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* +-----------------+-----+------------------------+-----+----+
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* | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
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* +-----------------------+------------------------+----------+
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*/
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static void disas_exc(DisasContext *s, uint32_t insn)
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static bool trans_SVC(DisasContext *s, arg_i *a)
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{
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int opc = extract32(insn, 21, 3);
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int op2_ll = extract32(insn, 0, 5);
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int imm16 = extract32(insn, 5, 16);
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uint32_t syndrome;
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switch (opc) {
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case 0:
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/* For SVC, HVC and SMC we advance the single-step state
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* machine before taking the exception. This is architecturally
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* mandated, to ensure that single-stepping a system call
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* instruction works properly.
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*/
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switch (op2_ll) {
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case 1: /* SVC */
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syndrome = syn_aa64_svc(imm16);
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if (s->fgt_svc) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
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break;
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}
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gen_ss_advance(s);
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gen_exception_insn(s, 4, EXCP_SWI, syndrome);
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break;
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case 2: /* HVC */
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if (s->current_el == 0) {
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unallocated_encoding(s);
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break;
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}
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/* The pre HVC helper handles cases when HVC gets trapped
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* as an undefined insn by runtime configuration.
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*/
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gen_a64_update_pc(s, 0);
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gen_helper_pre_hvc(cpu_env);
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gen_ss_advance(s);
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gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2);
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break;
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case 3: /* SMC */
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if (s->current_el == 0) {
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unallocated_encoding(s);
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break;
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}
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gen_a64_update_pc(s, 0);
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
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gen_ss_advance(s);
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gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3);
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break;
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default:
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unallocated_encoding(s);
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break;
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}
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break;
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case 1:
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if (op2_ll != 0) {
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unallocated_encoding(s);
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break;
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}
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/* BRK */
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gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
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break;
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case 2:
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if (op2_ll != 0) {
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unallocated_encoding(s);
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break;
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}
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/* HLT. This has two purposes.
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* Architecturally, it is an external halting debug instruction.
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* Since QEMU doesn't implement external debug, we treat this as
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* it is required for halting debug disabled: it will UNDEF.
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* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
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*/
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if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) {
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gen_exception_internal_insn(s, EXCP_SEMIHOST);
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} else {
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unallocated_encoding(s);
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}
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break;
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case 5:
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if (op2_ll < 1 || op2_ll > 3) {
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unallocated_encoding(s);
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break;
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}
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/* DCPS1, DCPS2, DCPS3 */
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unallocated_encoding(s);
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break;
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default:
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unallocated_encoding(s);
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break;
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/*
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* For SVC, HVC and SMC we advance the single-step state
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* machine before taking the exception. This is architecturally
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* mandated, to ensure that single-stepping a system call
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* instruction works properly.
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*/
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uint32_t syndrome = syn_aa64_svc(a->imm);
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if (s->fgt_svc) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
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return true;
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}
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gen_ss_advance(s);
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gen_exception_insn(s, 4, EXCP_SWI, syndrome);
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return true;
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}
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/* Branches, exception generating and system instructions */
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static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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static bool trans_HVC(DisasContext *s, arg_i *a)
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{
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switch (extract32(insn, 25, 7)) {
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case 0x6a: /* Exception generation / System */
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if (insn & (1 << 24)) {
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unallocated_encoding(s);
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} else {
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disas_exc(s, insn);
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}
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break;
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default:
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if (s->current_el == 0) {
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unallocated_encoding(s);
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break;
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return true;
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}
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/*
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* The pre HVC helper handles cases when HVC gets trapped
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* as an undefined insn by runtime configuration.
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*/
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gen_a64_update_pc(s, 0);
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gen_helper_pre_hvc(cpu_env);
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/* Architecture requires ss advance before we do the actual work */
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gen_ss_advance(s);
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gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2);
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return true;
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}
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static bool trans_SMC(DisasContext *s, arg_i *a)
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{
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if (s->current_el == 0) {
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unallocated_encoding(s);
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return true;
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}
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gen_a64_update_pc(s, 0);
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm)));
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/* Architecture requires ss advance before we do the actual work */
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gen_ss_advance(s);
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gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3);
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return true;
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}
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static bool trans_BRK(DisasContext *s, arg_i *a)
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{
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gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm));
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return true;
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}
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static bool trans_HLT(DisasContext *s, arg_i *a)
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{
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/*
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* HLT. This has two purposes.
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* Architecturally, it is an external halting debug instruction.
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* Since QEMU doesn't implement external debug, we treat this as
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* it is required for halting debug disabled: it will UNDEF.
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* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
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*/
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if (semihosting_enabled(s->current_el == 0) && a->imm == 0xf000) {
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gen_exception_internal_insn(s, EXCP_SEMIHOST);
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} else {
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unallocated_encoding(s);
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}
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return true;
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}
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/*
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@ -14188,9 +14146,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
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static void disas_a64_legacy(DisasContext *s, uint32_t insn)
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{
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switch (extract32(insn, 25, 4)) {
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case 0xa: case 0xb: /* Branch, exception generation and system insns */
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disas_b_exc_sys(s, insn);
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break;
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case 0x4:
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case 0x6:
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case 0xc:
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