From a83bddd60de0dfdbc04c6683c2701682073af5cf Mon Sep 17 00:00:00 2001
From: Dongxue Zhang <elta.era@gmail.com>
Date: Tue, 29 Jul 2014 21:48:10 +0800
Subject: [PATCH] target-mips/translate.c: Update OPC_SYNCI
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: update microMIPS SYNCI as well]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 57c2d414d6..7b9e8cd374 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13190,6 +13190,9 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
gen_logic_imm(ctx, OPC_LUI, rs, -1, imm);
break;
case SYNCI:
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case BC2F:
case BC2T:
@@ -16928,7 +16931,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
- /* Treat as NOP. */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)