mirror of https://github.com/xemu-project/xemu.git
target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK
For that move the definition from kvm.c to cpu.h Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170509082800.10756-2-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -1078,6 +1078,9 @@ struct sysib_322 {
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#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
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#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
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/* SIGP order code mask corresponding to bit positions 56-63 */
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#define SIGP_ORDER_MASK 0x000000ff
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void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, bool exc);
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@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
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return SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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#define SIGP_ORDER_MASK 0x000000ff
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static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
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{
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CPUS390XState *env = &cpu->env;
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@ -517,8 +517,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
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/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
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as parameter (input). Status (output) is always R1. */
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/* sigp contains the order code in bit positions 56-63, mask it here. */
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switch (order_code & 0xff) {
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switch (order_code & SIGP_ORDER_MASK) {
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case SIGP_SET_ARCH:
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/* switch arch */
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break;
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