mirror of https://github.com/xemu-project/xemu.git
target/sparc: Drop ifdef around get_asi and friends
Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
811cc0b0ce
commit
a76779ee3b
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@ -1900,7 +1900,6 @@ static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
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}
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/* asi moves */
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#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
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typedef enum {
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GET_ASI_HELPER,
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GET_ASI_EXCP,
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@ -2149,8 +2148,22 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
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return resolve_asi(dc, asi, memop);
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}
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static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
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int insn, MemOp memop)
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#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
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static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
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TCGv_i32 asi, TCGv_i32 mop)
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{
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g_assert_not_reached();
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}
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static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,
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TCGv_i32 asi, TCGv_i32 mop)
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{
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g_assert_not_reached();
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}
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#endif
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static void __attribute__((unused))
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gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
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{
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DisasASI da = get_asi(dc, insn, memop);
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@ -2184,8 +2197,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
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}
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}
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static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
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int insn, MemOp memop)
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static void __attribute__((unused))
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gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
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{
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DisasASI da = get_asi(dc, insn, memop);
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@ -2260,8 +2273,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
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}
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}
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static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
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TCGv addr, int insn)
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static void __attribute__((unused))
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gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUL);
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@ -2278,8 +2291,8 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
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}
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}
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static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
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int insn, int rd)
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static void __attribute__((unused))
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gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUL);
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TCGv oldv;
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@ -2300,7 +2313,8 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
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}
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}
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static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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static void __attribute__((unused))
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gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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{
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DisasASI da = get_asi(dc, insn, MO_UB);
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@ -2335,11 +2349,9 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
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break;
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}
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}
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#endif
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#ifdef TARGET_SPARC64
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static void gen_ldf_asi(DisasContext *dc, TCGv addr,
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int insn, int size, int rd)
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static void __attribute__((unused))
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gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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{
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DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
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TCGv_i32 d32;
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@ -2447,8 +2459,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
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}
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}
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static void gen_stf_asi(DisasContext *dc, TCGv addr,
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int insn, int size, int rd)
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static void __attribute__((unused))
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gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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{
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DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
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TCGv_i32 d32;
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@ -2530,21 +2542,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
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}
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}
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static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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static void __attribute__((unused))
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gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv_i64 hi = gen_dest_gpr(dc, rd);
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TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
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TCGv hi = gen_dest_gpr(dc, rd);
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TCGv lo = gen_dest_gpr(dc, rd + 1);
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switch (da.type) {
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case GET_ASI_EXCP:
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return;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop);
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break;
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case GET_ASI_DIRECT:
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@ -2558,9 +2572,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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result is byte swapped. Having just performed one
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64-bit bswap, we need now to swap the writebacks. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr32_i64(lo, hi, tmp);
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tcg_gen_extr_i64_tl(lo, hi, tmp);
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} else {
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tcg_gen_extr32_i64(hi, lo, tmp);
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tcg_gen_extr_i64_tl(hi, lo, tmp);
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}
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}
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break;
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@ -2580,9 +2594,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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/* See above. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr32_i64(lo, hi, tmp);
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tcg_gen_extr_i64_tl(lo, hi, tmp);
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} else {
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tcg_gen_extr32_i64(hi, lo, tmp);
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tcg_gen_extr_i64_tl(hi, lo, tmp);
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}
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}
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break;
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@ -2592,8 +2606,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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gen_store_gpr(dc, rd + 1, lo);
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}
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static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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int insn, int rd)
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static void __attribute__((unused))
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gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv lo = gen_load_gpr(dc, rd + 1);
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@ -2603,10 +2617,11 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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break;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
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tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop);
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break;
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case GET_ASI_DIRECT:
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@ -2617,15 +2632,37 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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byte swapped. We will perform one 64-bit LE store, so now
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we must swap the order of the construction. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_concat32_i64(t64, lo, hi);
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tcg_gen_concat_tl_i64(t64, lo, hi);
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} else {
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tcg_gen_concat32_i64(t64, hi, lo);
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tcg_gen_concat_tl_i64(t64, hi, lo);
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}
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
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}
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break;
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case GET_ASI_BFILL:
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assert(TARGET_LONG_BITS == 32);
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/* Store 32 bytes of T64 to ADDR. */
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/* ??? The original qemu code suggests 8-byte alignment, dropping
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the low bits, but the only place I can see this used is in the
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Linux kernel with 32 byte alignment, which would make more sense
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as a cacheline-style operation. */
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{
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TCGv_i64 t64 = tcg_temp_new_i64();
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TCGv d_addr = tcg_temp_new();
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TCGv eight = tcg_constant_tl(8);
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int i;
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tcg_gen_concat_tl_i64(t64, lo, hi);
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tcg_gen_andi_tl(d_addr, addr, -8);
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for (i = 0; i < 32; i += 8) {
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tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
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tcg_gen_add_tl(d_addr, d_addr, eight);
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}
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}
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break;
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default:
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/* ??? In theory we've handled all of the ASIs that are valid
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for stda, and this should raise DAE_invalid_asi. */
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@ -2636,9 +2673,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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/* See above. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_concat32_i64(t64, lo, hi);
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tcg_gen_concat_tl_i64(t64, lo, hi);
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} else {
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tcg_gen_concat32_i64(t64, hi, lo);
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tcg_gen_concat_tl_i64(t64, hi, lo);
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}
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save_state(dc);
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@ -2648,8 +2685,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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}
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}
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static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
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int insn, int rd)
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static void __attribute__((unused))
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gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv oldv;
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@ -2670,88 +2707,6 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
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}
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}
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#elif !defined(CONFIG_USER_ONLY)
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static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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{
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/* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
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whereby "rd + 1" elicits "error: array subscript is above array".
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Since we have already asserted that rd is even, the semantics
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are unchanged. */
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TCGv lo = gen_dest_gpr(dc, rd | 1);
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TCGv hi = gen_dest_gpr(dc, rd);
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TCGv_i64 t64 = tcg_temp_new_i64();
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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switch (da.type) {
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case GET_ASI_EXCP:
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return;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(MO_UQ);
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save_state(dc);
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gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
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}
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break;
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}
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tcg_gen_extr_i64_i32(lo, hi, t64);
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gen_store_gpr(dc, rd | 1, lo);
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gen_store_gpr(dc, rd, hi);
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}
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static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEUQ);
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TCGv lo = gen_load_gpr(dc, rd + 1);
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_concat_tl_i64(t64, lo, hi);
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switch (da.type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
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break;
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case GET_ASI_BFILL:
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/* Store 32 bytes of T64 to ADDR. */
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/* ??? The original qemu code suggests 8-byte alignment, dropping
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the low bits, but the only place I can see this used is in the
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Linux kernel with 32 byte alignment, which would make more sense
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as a cacheline-style operation. */
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{
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TCGv d_addr = tcg_temp_new();
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TCGv eight = tcg_constant_tl(8);
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int i;
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tcg_gen_andi_tl(d_addr, addr, -8);
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for (i = 0; i < 32; i += 8) {
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tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
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tcg_gen_add_tl(d_addr, d_addr, eight);
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}
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}
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(MO_UQ);
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save_state(dc);
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gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
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}
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break;
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}
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}
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#endif
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static TCGv get_src1(DisasContext *dc, unsigned int insn)
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{
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unsigned int rs1 = GET_FIELD(insn, 13, 17);
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