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hw/misc/mps2-scc: Fix condition for CFG3 register 

We currently guard the CFG3 register read with
 (scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
which is clearly wrong as it is never true.

This register is present on all board types except AN524
and AN527; correct the condition.

Fixes: 6ac8081894 ("hw/misc/mps2-scc: Implement changes for AN547")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-02-06 13:29:23 +00:00
parent f2b4a98930
commit a72e625078
1 changed files with 1 additions and 1 deletions
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2
hw/misc/mps2-scc.c
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@ -118,7 +118,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
r = s->cfg2;
break;
case A_CFG3:
if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
/* CFG3 reserved on AN524 */
goto bad_offset;
}