mirror of https://github.com/xemu-project/xemu.git
Add more machine definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4020 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
18be8d775e
commit
a526a31cb4
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@ -53,6 +53,8 @@ extern QEMUMachine r2d_machine;
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/* sun4m.c */
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/* sun4m.c */
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extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
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extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine, ss20_machine;
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extern QEMUMachine voyager_machine, ss_lx_machine, ss4_machine, scls_machine;
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extern QEMUMachine sbook_machine;
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extern QEMUMachine ss2_machine;
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extern QEMUMachine ss2_machine;
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extern QEMUMachine ss1000_machine, ss2000_machine;
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extern QEMUMachine ss1000_machine, ss2000_machine;
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290
hw/sun4m.c
290
hw/sun4m.c
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@ -891,6 +891,216 @@ static const struct hwdef hwdefs[] = {
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.max_mem = 0x10000000,
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.max_mem = 0x10000000,
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.default_cpu_model = "Cypress CY7C601",
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.default_cpu_model = "Cypress CY7C601",
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},
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},
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/* Voyager */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.cs_base = -1,
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.slavio_base = 0x70000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.idreg_base = 0x78000000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = 0x71300000, // pmc
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "Fujitsu MB86904",
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},
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/* LX */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.cs_base = -1,
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.slavio_base = 0x70000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.idreg_base = 0x78000000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = -1,
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.iommu_version = 0x04000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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/* SS-4 */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.cs_base = 0x6c000000,
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.slavio_base = 0x70000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.idreg_base = 0x78000000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = 0x6a000000,
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = 5,
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.machine_id = 0x80,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "Fujitsu MB86904",
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},
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/* SPARCClassic */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.cs_base = -1,
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.slavio_base = 0x70000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.idreg_base = 0x78000000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = 0x6a000000,
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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/* SPARCbook */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000, // XXX
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.cs_base = -1,
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.slavio_base = 0x70000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.idreg_base = 0x78000000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = 0x6a000000,
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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};
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};
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/* SPARCstation 5 hardware initialisation */
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/* SPARCstation 5 hardware initialisation */
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@ -943,6 +1153,56 @@ static void ss2_init(int RAM_size, int vga_ram_size,
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kernel_cmdline, initrd_filename, cpu_model);
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kernel_cmdline, initrd_filename, cpu_model);
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}
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}
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/* SPARCstation Voyager hardware initialisation */
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static void vger_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCstation LX hardware initialisation */
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static void ss_lx_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCstation 4 hardware initialisation */
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static void ss4_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCClassic hardware initialisation */
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static void scls_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCbook hardware initialisation */
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static void sbook_init(int RAM_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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QEMUMachine ss5_machine = {
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QEMUMachine ss5_machine = {
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"SS-5",
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"SS-5",
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"Sun4m platform, SPARCstation 5",
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"Sun4m platform, SPARCstation 5",
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@ -973,6 +1233,36 @@ QEMUMachine ss2_machine = {
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ss2_init,
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ss2_init,
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};
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};
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QEMUMachine voyager_machine = {
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"Voyager",
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"Sun4m platform, SPARCstation Voyager",
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vger_init,
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};
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QEMUMachine ss_lx_machine = {
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"LX",
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"Sun4m platform, SPARCstation LX",
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ss_lx_init,
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};
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QEMUMachine ss4_machine = {
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"SS-4",
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"Sun4m platform, SPARCstation 4",
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ss4_init,
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};
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QEMUMachine scls_machine = {
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"SPARCClassic",
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"Sun4m platform, SPARCClassic",
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scls_init,
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};
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QEMUMachine sbook_machine = {
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"SPARCbook",
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"Sun4m platform, SPARCbook",
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sbook_init,
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};
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static const struct sun4d_hwdef sun4d_hwdefs[] = {
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static const struct sun4d_hwdef sun4d_hwdefs[] = {
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/* SS-1000 */
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/* SS-1000 */
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{
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{
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5
vl.c
5
vl.c
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@ -7988,6 +7988,11 @@ static void register_machines(void)
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qemu_register_machine(&ss600mp_machine);
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qemu_register_machine(&ss600mp_machine);
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qemu_register_machine(&ss20_machine);
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qemu_register_machine(&ss20_machine);
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qemu_register_machine(&ss2_machine);
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qemu_register_machine(&ss2_machine);
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qemu_register_machine(&voyager_machine);
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qemu_register_machine(&ss_lx_machine);
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qemu_register_machine(&ss4_machine);
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qemu_register_machine(&scls_machine);
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qemu_register_machine(&sbook_machine);
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qemu_register_machine(&ss1000_machine);
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qemu_register_machine(&ss1000_machine);
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qemu_register_machine(&ss2000_machine);
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qemu_register_machine(&ss2000_machine);
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#endif
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#endif
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