ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/loongarch: Implement vsrlrn vsrarn 

This patch includes:
- VSRLRN.{B.H/H.W/W.D};
- VSRARN.{B.H/H.W/W.D};
- VSRLRNI.{B.H/H.W/W.D/D.Q};
- VSRARNI.{B.H/H.W/W.D/D.Q}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-27-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:52 +08:00
parent d79fb8ddcd
commit a5200a17c9
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 190 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
target/loongarch/disas.c
View File

@ -1182,3 +1182,19 @@ INSN_LSX(vsrani_b_h, vv_i)
INSN_LSX(vsrani_h_w, vv_i)
INSN_LSX(vsrani_w_d, vv_i)
INSN_LSX(vsrani_d_q, vv_i)
INSN_LSX(vsrlrn_b_h, vvv)
INSN_LSX(vsrlrn_h_w, vvv)
INSN_LSX(vsrlrn_w_d, vvv)
INSN_LSX(vsrarn_b_h, vvv)
INSN_LSX(vsrarn_h_w, vvv)
INSN_LSX(vsrarn_w_d, vvv)
INSN_LSX(vsrlrni_b_h, vv_i)
INSN_LSX(vsrlrni_h_w, vv_i)
INSN_LSX(vsrlrni_w_d, vv_i)
INSN_LSX(vsrlrni_d_q, vv_i)
INSN_LSX(vsrarni_b_h, vv_i)
INSN_LSX(vsrarni_h_w, vv_i)
INSN_LSX(vsrarni_w_d, vv_i)
INSN_LSX(vsrarni_d_q, vv_i)

16
target/loongarch/helper.h
View File

@ -395,3 +395,19 @@ DEF_HELPER_4(vsrani_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrn_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_d_q, void, env, i32, i32, i32)

16
target/loongarch/insn_trans/trans_lsx.c.inc
View File

@ -3021,3 +3021,19 @@ TRANS(vsrani_b_h, gen_vv_i, gen_helper_vsrani_b_h)
TRANS(vsrani_h_w, gen_vv_i, gen_helper_vsrani_h_w)
TRANS(vsrani_w_d, gen_vv_i, gen_helper_vsrani_w_d)
TRANS(vsrani_d_q, gen_vv_i, gen_helper_vsrani_d_q)
TRANS(vsrlrn_b_h, gen_vvv, gen_helper_vsrlrn_b_h)
TRANS(vsrlrn_h_w, gen_vvv, gen_helper_vsrlrn_h_w)
TRANS(vsrlrn_w_d, gen_vvv, gen_helper_vsrlrn_w_d)
TRANS(vsrarn_b_h, gen_vvv, gen_helper_vsrarn_b_h)
TRANS(vsrarn_h_w, gen_vvv, gen_helper_vsrarn_h_w)
TRANS(vsrarn_w_d, gen_vvv, gen_helper_vsrarn_w_d)
TRANS(vsrlrni_b_h, gen_vv_i, gen_helper_vsrlrni_b_h)
TRANS(vsrlrni_h_w, gen_vv_i, gen_helper_vsrlrni_h_w)
TRANS(vsrlrni_w_d, gen_vv_i, gen_helper_vsrlrni_w_d)
TRANS(vsrlrni_d_q, gen_vv_i, gen_helper_vsrlrni_d_q)
TRANS(vsrarni_b_h, gen_vv_i, gen_helper_vsrarni_b_h)
TRANS(vsrarni_h_w, gen_vv_i, gen_helper_vsrarni_h_w)
TRANS(vsrarni_w_d, gen_vv_i, gen_helper_vsrarni_w_d)
TRANS(vsrarni_d_q, gen_vv_i, gen_helper_vsrarni_d_q)

16
target/loongarch/insns.decode
View File

@ -883,3 +883,19 @@ vsrani_b_h 0111 00110101 10000 1 .... ..... ..... @vv_ui4
vsrani_h_w 0111 00110101 10001 ..... ..... ..... @vv_ui5
vsrani_w_d 0111 00110101 1001 ...... ..... ..... @vv_ui6
vsrani_d_q 0111 00110101 101 ....... ..... ..... @vv_ui7
vsrlrn_b_h 0111 00001111 10001 ..... ..... ..... @vvv
vsrlrn_h_w 0111 00001111 10010 ..... ..... ..... @vvv
vsrlrn_w_d 0111 00001111 10011 ..... ..... ..... @vvv
vsrarn_b_h 0111 00001111 10101 ..... ..... ..... @vvv
vsrarn_h_w 0111 00001111 10110 ..... ..... ..... @vvv
vsrarn_w_d 0111 00001111 10111 ..... ..... ..... @vvv
vsrlrni_b_h 0111 00110100 01000 1 .... ..... ..... @vv_ui4
vsrlrni_h_w 0111 00110100 01001 ..... ..... ..... @vv_ui5
vsrlrni_w_d 0111 00110100 0101 ...... ..... ..... @vv_ui6
vsrlrni_d_q 0111 00110100 011 ....... ..... ..... @vv_ui7
vsrarni_b_h 0111 00110101 11000 1 .... ..... ..... @vv_ui4
vsrarni_h_w 0111 00110101 11001 ..... ..... ..... @vv_ui5
vsrarni_w_d 0111 00110101 1101 ...... ..... ..... @vv_ui6
vsrarni_d_q 0111 00110101 111 ....... ..... ..... @vv_ui7

126
target/loongarch/lsx_helper.c
View File

@ -1052,3 +1052,129 @@ void HELPER(vsrani_d_q)(CPULoongArchState *env,
VSRANI(vsrani_b_h, 16, B, H)
VSRANI(vsrani_h_w, 32, H, W)
VSRANI(vsrani_w_d, 64, W, D)
#define VSRLRN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = do_vsrlr_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
} \
Vd->D(1) = 0; \
}
VSRLRN(vsrlrn_b_h, 16, uint16_t, B, H)
VSRLRN(vsrlrn_h_w, 32, uint32_t, H, W)
VSRLRN(vsrlrn_w_d, 64, uint64_t, W, D)
#define VSRARN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = do_vsrar_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
} \
Vd->D(1) = 0; \
}
VSRARN(vsrarn_b_h, 16, uint8_t, B, H)
VSRARN(vsrarn_h_w, 32, uint16_t, H, W)
VSRARN(vsrarn_w_d, 64, uint32_t, W, D)
#define VSRLRNI(NAME, BIT, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t imm) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = do_vsrlr_ ## E2(Vj->E2(i), imm); \
temp.E1(i + max) = do_vsrlr_ ## E2(Vd->E2(i), imm); \
} \
*Vd = temp; \
}
void HELPER(vsrlrni_d_q)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
Int128 r1, r2;
if (imm == 0) {
temp.D(0) = int128_getlo(Vj->Q(0));
temp.D(1) = int128_getlo(Vd->Q(0));
} else {
r1 = int128_and(int128_urshift(Vj->Q(0), (imm -1)), int128_one());
r2 = int128_and(int128_urshift(Vd->Q(0), (imm -1)), int128_one());
temp.D(0) = int128_getlo(int128_add(int128_urshift(Vj->Q(0), imm), r1));
temp.D(1) = int128_getlo(int128_add(int128_urshift(Vd->Q(0), imm), r2));
}
*Vd = temp;
}
VSRLRNI(vsrlrni_b_h, 16, B, H)
VSRLRNI(vsrlrni_h_w, 32, H, W)
VSRLRNI(vsrlrni_w_d, 64, W, D)
#define VSRARNI(NAME, BIT, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t imm) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = do_vsrar_ ## E2(Vj->E2(i), imm); \
temp.E1(i + max) = do_vsrar_ ## E2(Vd->E2(i), imm); \
} \
*Vd = temp; \
}
void HELPER(vsrarni_d_q)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
Int128 r1, r2;
if (imm == 0) {
temp.D(0) = int128_getlo(Vj->Q(0));
temp.D(1) = int128_getlo(Vd->Q(0));
} else {
r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
temp.D(0) = int128_getlo(int128_add(int128_rshift(Vj->Q(0), imm), r1));
temp.D(1) = int128_getlo(int128_add(int128_rshift(Vd->Q(0), imm), r2));
}
*Vd = temp;
}
VSRARNI(vsrarni_b_h, 16, B, H)
VSRARNI(vsrarni_h_w, 32, H, W)
VSRARNI(vsrarni_w_d, 64, W, D)