mirror of https://github.com/xemu-project/xemu.git
hw/acpi: add _CRS method for extra root busses
Save the IO/mem/bus numbers ranges assigned to the extra root busses to be removed from the root bus 0 range. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
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0d8935e337
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@ -697,6 +697,137 @@ static Aml *build_prt(void)
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return method;
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}
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typedef struct CrsRangeEntry {
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uint64_t base;
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uint64_t limit;
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} CrsRangeEntry;
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static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
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{
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CrsRangeEntry *entry;
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entry = g_malloc(sizeof(*entry));
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entry->base = base;
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entry->limit = limit;
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g_ptr_array_add(ranges, entry);
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}
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static void crs_range_free(gpointer data)
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{
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CrsRangeEntry *entry = (CrsRangeEntry *)data;
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g_free(entry);
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}
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static Aml *build_crs(PCIHostState *host,
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GPtrArray *io_ranges, GPtrArray *mem_ranges)
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{
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Aml *crs = aml_resource_template();
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uint8_t max_bus = pci_bus_num(host->bus);
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uint8_t type;
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int devfn;
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for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
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int i;
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uint64_t range_base, range_limit;
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PCIDevice *dev = host->bus->devices[devfn];
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if (!dev) {
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continue;
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}
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for (i = 0; i < PCI_NUM_REGIONS; i++) {
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PCIIORegion *r = &dev->io_regions[i];
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range_base = r->addr;
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range_limit = r->addr + r->size - 1;
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if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0,
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range_base,
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range_limit,
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0,
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range_limit - range_base + 1));
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crs_range_insert(io_ranges, range_base, range_limit);
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} else { /* "memory" */
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed,
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aml_max_fixed, aml_non_cacheable,
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aml_ReadWrite,
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0,
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range_base,
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range_limit,
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0,
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range_limit - range_base + 1));
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crs_range_insert(mem_ranges, range_base, range_limit);
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}
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}
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type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
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if (type == PCI_HEADER_TYPE_BRIDGE) {
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uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
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if (subordinate > max_bus) {
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max_bus = subordinate;
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}
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range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
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range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0,
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range_base,
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range_limit,
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0,
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range_limit - range_base + 1));
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crs_range_insert(io_ranges, range_base, range_limit);
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range_base =
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pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
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range_limit =
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pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed,
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aml_max_fixed, aml_non_cacheable,
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aml_ReadWrite,
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0,
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range_base,
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range_limit,
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0,
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range_limit - range_base + 1));
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crs_range_insert(mem_ranges, range_base, range_limit);
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range_base =
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pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
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range_limit =
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pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed,
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aml_max_fixed, aml_non_cacheable,
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aml_ReadWrite,
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0,
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range_base,
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range_limit,
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0,
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range_limit - range_base + 1));
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crs_range_insert(mem_ranges, range_base, range_limit);
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}
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}
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aml_append(crs,
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aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
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0,
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pci_bus_num(host->bus),
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max_bus,
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0,
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max_bus - pci_bus_num(host->bus) + 1));
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return crs;
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}
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static void
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build_ssdt(GArray *table_data, GArray *linker,
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AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
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@ -707,6 +838,8 @@ build_ssdt(GArray *table_data, GArray *linker,
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unsigned acpi_cpus = guest_info->apic_id_limit;
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Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
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PCIBus *bus = NULL;
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GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
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int i;
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ssdt = init_aml_allocator();
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@ -736,9 +869,15 @@ build_ssdt(GArray *table_data, GArray *linker,
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
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aml_append(dev, build_prt());
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crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
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io_ranges, mem_ranges);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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aml_append(ssdt, scope);
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}
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g_ptr_array_free(io_ranges, true);
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g_ptr_array_free(mem_ranges, true);
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}
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scope = aml_scope("\\_SB.PCI0");
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