mirror of https://github.com/xemu-project/xemu.git
target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2
The syndrome value reported to ESR_EL2 should only contain the detailed instruction syndrome information when the fault has been caused by a stage 2 abort, not when the fault was a stage 1 abort (i.e. caused by execution at EL2). We were getting this wrong and reporting the detailed ISV information all the time. Fix the bug by checking fi->stage2. Add a TODO comment noting the cases where we'll have to come back and revisit this when we implement FEAT_LS64 and friends. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230331145045.2584941-3-peter.maydell@linaro.org
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@ -32,8 +32,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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uint32_t syn;
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/*
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* ISV is only set for data aborts routed to EL2 and
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* never for stage-1 page table walks faulting on stage 2.
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* ISV is only set for stage-2 data aborts routed to EL2 and
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* never for stage-1 page table walks faulting on stage 2
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* or for stage-1 faults.
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*
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* Furthermore, ISV is only set for certain kinds of load/stores.
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* If the template syndrome does not have ISV set, we should leave
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@ -42,8 +43,14 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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* See ARMv8 specs, D7-1974:
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* ISS encoding for an exception from a Data Abort, the
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* ISV field.
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*
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* TODO: FEAT_LS64/FEAT_LS64_V/FEAT_SL64_ACCDATA: Translation,
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* Access Flag, and Permission faults caused by LD64B, ST64B,
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* ST64BV, or ST64BV0 insns report syndrome info even for stage-1
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* faults and regardless of the target EL.
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*/
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if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) {
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if (!(template_syn & ARM_EL_ISV) || target_el != 2
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|| fi->s1ptw || !fi->stage2) {
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syn = syn_data_abort_no_iss(same_el, 0,
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fi->ea, 0, fi->s1ptw, is_write, fsc);
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} else {
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