From b6d9766ddf5453e79e0c66c9348728ba44ba115f Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 21 Aug 2013 08:54:29 +0800 Subject: [PATCH 1/3] hw/openrisc: Avoid using uninitialised variable 'entry' clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized: hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used uninitialized whenever '&&' condition is false [-Werror,-Wsometimes-uninitialized] if (kernel_filename && !qtest_enabled()) { ^~~~~~~~~~~~~~~ hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here cpu->env.pc = entry; ^~~~~ Fix this by not attempting to change the CPU's starting PC unless we actually loaded a kernel. Signed-off-by: Peter Maydell Reviewed-by: Jia Liu --- hw/openrisc/openrisc_sim.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index a08f27ce2e..28fa41d64e 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -86,9 +86,8 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_filename); exit(1); } + cpu->env.pc = entry; } - - cpu->env.pc = entry; } static void openrisc_sim_init(QEMUMachineInitArgs *args) From ed396e2b2d256c1628de7c11841b509455a76c03 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 21 Aug 2013 09:23:10 +0800 Subject: [PATCH 2/3] hw/openrisc: Fix masking in openrisc_pic_cpu_handler() Consider the masking of PICSR and PICMR: ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) To correctly mask bits, we should use the bitwise AND "&" rather than the logical AND "&&". Also, the loop is not necessary for masking. Simply use (cpu->env.picsr & cpu->env.picmr). Signed-off-by: Xi Wang Acked-by: Jia Liu --- hw/openrisc/pic_cpu.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index ca0b7c11bd..3fcee02619 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; CPUState *cs = CPU(cpu); - int i; uint32_t irq_bit = 1 << irq; if (irq > 31 || irq < 0) { @@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) cpu->env.picsr &= ~irq_bit; } - for (i = 0; i < 32; i++) { - if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr &= ~(1 << i); - } + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr = 0; } } From 7717f248eebdcfe6de400404d0cf65dcb3633308 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 21 Aug 2013 09:31:36 +0800 Subject: [PATCH 3/3] hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() In C99 signed shift (1 << 31) is undefined behavior, since the result exceeds INT_MAX. Use 1U instead and move the shift after the check. Signed-off-by: Xi Wang Acked-by: Jia Liu --- hw/openrisc/pic_cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index 3fcee02619..2af1d6013a 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; CPUState *cs = CPU(cpu); - uint32_t irq_bit = 1 << irq; + uint32_t irq_bit; if (irq > 31 || irq < 0) { return; } + irq_bit = 1U << irq; + if (level) { cpu->env.picsr |= irq_bit; } else {