From 9ef2629712680e70cbf39d8b6cb1ec0e0e2e72fa Mon Sep 17 00:00:00 2001 From: Chris Rauer Date: Fri, 22 Sep 2023 18:14:11 +0000 Subject: [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero The counter register is only 24-bits and counts down. If the timer is running but the qtimer to reset it hasn't fired off yet, there is a chance the regster read can return an invalid result. Signed-off-by: Chris Rauer Message-id: 20230922181411.2697135-1-crauer@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/npcm7xx_timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 32f5e021f8..a8bd93aeb2 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -138,6 +138,9 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { + if (ns < 0) { + return 0; + } return clock_ns_to_ticks(t->ctrl->clock, ns) / npcm7xx_tcsr_prescaler(t->tcsr); }