mirror of https://github.com/xemu-project/xemu.git
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
This model implementation is designed for 32-bit accesses. We can simplify setting the MemoryRegionOps::impl min/max fields to 32-bit (memory::access_with_adjusted_size() will take care of the 8/16-bit accesses). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200901144100.116742-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -28,12 +28,6 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
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return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
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case 0x08: /* CPU Power Status */
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return s->status;
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case 0x09: /* CPU status. */
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return s->status >> 8;
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case 0x0a: /* CPU status. */
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return s->status >> 16;
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case 0x0b: /* CPU status. */
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return s->status >> 24;
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case 0x0c: /* Invalidate All Registers In Secure State */
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return 0;
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case 0x40: /* Filtering Start Address Register */
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@ -52,8 +46,6 @@ static void a9_scu_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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A9SCUState *s = (A9SCUState *)opaque;
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uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
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uint32_t shift;
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switch (offset) {
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case 0x00: /* Control */
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@ -62,9 +54,7 @@ static void a9_scu_write(void *opaque, hwaddr offset,
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case 0x4: /* Configuration: RO */
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break;
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case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
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shift = (offset - 0x8) * 8;
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s->status &= ~(mask << shift);
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s->status |= ((value & mask) << shift);
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s->status = value;
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break;
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case 0x0c: /* Invalidate All Registers In Secure State */
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/* no-op as we do not implement caches */
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@ -84,6 +74,10 @@ static void a9_scu_write(void *opaque, hwaddr offset,
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static const MemoryRegionOps a9_scu_ops = {
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.read = a9_scu_read,
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.write = a9_scu_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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