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target/alpha: Honor the FEN bit 

This bit is used by NetBSD for lazy fpu migration.

Tested-by: Jason Thorpe <thorpej@me.com>
Reported-by: Jason Thorpe <thorpej@me.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/438
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-06-21 10:02:34 -07:00
parent c6446a1b6d
commit 9d14a04280
1 changed files with 75 additions and 0 deletions
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75
target/alpha/translate.c
View File

@ -1471,6 +1471,13 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
} \ } \
} while (0) } while (0)
#define REQUIRE_FEN \
do { \
if (!(ctx->tbflags & ENV_FLAG_FEN)) { \
goto raise_fen; \
} \
} while (0)
static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
{ {
int32_t disp21, disp16, disp12 __attribute__((unused)); int32_t disp21, disp16, disp12 __attribute__((unused));
@ -2066,6 +2073,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x04: case 0x04:
/* ITOFS */ /* ITOFS */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
REQUIRE_FEN;
t32 = tcg_temp_new_i32(); t32 = tcg_temp_new_i32();
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
tcg_gen_extrl_i64_i32(t32, va); tcg_gen_extrl_i64_i32(t32, va);
@ -2075,17 +2083,20 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x0A: case 0x0A:
/* SQRTF */ /* SQRTF */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_sqrtf(vc, cpu_env, vb); gen_helper_sqrtf(vc, cpu_env, vb);
break; break;
case 0x0B: case 0x0B:
/* SQRTS */ /* SQRTS */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_sqrts(ctx, rb, rc, fn11); gen_sqrts(ctx, rb, rc, fn11);
break; break;
case 0x14: case 0x14:
/* ITOFF */ /* ITOFF */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
REQUIRE_FEN;
t32 = tcg_temp_new_i32(); t32 = tcg_temp_new_i32();
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
tcg_gen_extrl_i64_i32(t32, va); tcg_gen_extrl_i64_i32(t32, va);
@ -2095,18 +2106,21 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x24: case 0x24:
/* ITOFT */ /* ITOFT */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
REQUIRE_FEN;
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
tcg_gen_mov_i64(vc, va); tcg_gen_mov_i64(vc, va);
break; break;
case 0x2A: case 0x2A:
/* SQRTG */ /* SQRTG */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_sqrtg(vc, cpu_env, vb); gen_helper_sqrtg(vc, cpu_env, vb);
break; break;
case 0x02B: case 0x02B:
/* SQRTT */ /* SQRTT */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_sqrtt(ctx, rb, rc, fn11); gen_sqrtt(ctx, rb, rc, fn11);
break; break;
default: default:
@ -2123,18 +2137,22 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
switch (fpfn) { /* fn11 & 0x3F */ switch (fpfn) { /* fn11 & 0x3F */
case 0x00: case 0x00:
/* ADDF */ /* ADDF */
REQUIRE_FEN;
gen_helper_addf(vc, cpu_env, va, vb); gen_helper_addf(vc, cpu_env, va, vb);
break; break;
case 0x01: case 0x01:
/* SUBF */ /* SUBF */
REQUIRE_FEN;
gen_helper_subf(vc, cpu_env, va, vb); gen_helper_subf(vc, cpu_env, va, vb);
break; break;
case 0x02: case 0x02:
/* MULF */ /* MULF */
REQUIRE_FEN;
gen_helper_mulf(vc, cpu_env, va, vb); gen_helper_mulf(vc, cpu_env, va, vb);
break; break;
case 0x03: case 0x03:
/* DIVF */ /* DIVF */
REQUIRE_FEN;
gen_helper_divf(vc, cpu_env, va, vb); gen_helper_divf(vc, cpu_env, va, vb);
break; break;
case 0x1E: case 0x1E:
@ -2143,35 +2161,43 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc; goto invalid_opc;
case 0x20: case 0x20:
/* ADDG */ /* ADDG */
REQUIRE_FEN;
gen_helper_addg(vc, cpu_env, va, vb); gen_helper_addg(vc, cpu_env, va, vb);
break; break;
case 0x21: case 0x21:
/* SUBG */ /* SUBG */
REQUIRE_FEN;
gen_helper_subg(vc, cpu_env, va, vb); gen_helper_subg(vc, cpu_env, va, vb);
break; break;
case 0x22: case 0x22:
/* MULG */ /* MULG */
REQUIRE_FEN;
gen_helper_mulg(vc, cpu_env, va, vb); gen_helper_mulg(vc, cpu_env, va, vb);
break; break;
case 0x23: case 0x23:
/* DIVG */ /* DIVG */
REQUIRE_FEN;
gen_helper_divg(vc, cpu_env, va, vb); gen_helper_divg(vc, cpu_env, va, vb);
break; break;
case 0x25: case 0x25:
/* CMPGEQ */ /* CMPGEQ */
REQUIRE_FEN;
gen_helper_cmpgeq(vc, cpu_env, va, vb); gen_helper_cmpgeq(vc, cpu_env, va, vb);
break; break;
case 0x26: case 0x26:
/* CMPGLT */ /* CMPGLT */
REQUIRE_FEN;
gen_helper_cmpglt(vc, cpu_env, va, vb); gen_helper_cmpglt(vc, cpu_env, va, vb);
break; break;
case 0x27: case 0x27:
/* CMPGLE */ /* CMPGLE */
REQUIRE_FEN;
gen_helper_cmpgle(vc, cpu_env, va, vb); gen_helper_cmpgle(vc, cpu_env, va, vb);
break; break;
case 0x2C: case 0x2C:
/* CVTGF */ /* CVTGF */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgf(vc, cpu_env, vb); gen_helper_cvtgf(vc, cpu_env, vb);
break; break;
case 0x2D: case 0x2D:
@ -2181,16 +2207,19 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x2F: case 0x2F:
/* CVTGQ */ /* CVTGQ */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtgq(vc, cpu_env, vb); gen_helper_cvtgq(vc, cpu_env, vb);
break; break;
case 0x3C: case 0x3C:
/* CVTQF */ /* CVTQF */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqf(vc, cpu_env, vb); gen_helper_cvtqf(vc, cpu_env, vb);
break; break;
case 0x3E: case 0x3E:
/* CVTQG */ /* CVTQG */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_helper_cvtqg(vc, cpu_env, vb); gen_helper_cvtqg(vc, cpu_env, vb);
break; break;
default: default:
@ -2203,54 +2232,67 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
switch (fpfn) { /* fn11 & 0x3F */ switch (fpfn) { /* fn11 & 0x3F */
case 0x00: case 0x00:
/* ADDS */ /* ADDS */
REQUIRE_FEN;
gen_adds(ctx, ra, rb, rc, fn11); gen_adds(ctx, ra, rb, rc, fn11);
break; break;
case 0x01: case 0x01:
/* SUBS */ /* SUBS */
REQUIRE_FEN;
gen_subs(ctx, ra, rb, rc, fn11); gen_subs(ctx, ra, rb, rc, fn11);
break; break;
case 0x02: case 0x02:
/* MULS */ /* MULS */
REQUIRE_FEN;
gen_muls(ctx, ra, rb, rc, fn11); gen_muls(ctx, ra, rb, rc, fn11);
break; break;
case 0x03: case 0x03:
/* DIVS */ /* DIVS */
REQUIRE_FEN;
gen_divs(ctx, ra, rb, rc, fn11); gen_divs(ctx, ra, rb, rc, fn11);
break; break;
case 0x20: case 0x20:
/* ADDT */ /* ADDT */
REQUIRE_FEN;
gen_addt(ctx, ra, rb, rc, fn11); gen_addt(ctx, ra, rb, rc, fn11);
break; break;
case 0x21: case 0x21:
/* SUBT */ /* SUBT */
REQUIRE_FEN;
gen_subt(ctx, ra, rb, rc, fn11); gen_subt(ctx, ra, rb, rc, fn11);
break; break;
case 0x22: case 0x22:
/* MULT */ /* MULT */
REQUIRE_FEN;
gen_mult(ctx, ra, rb, rc, fn11); gen_mult(ctx, ra, rb, rc, fn11);
break; break;
case 0x23: case 0x23:
/* DIVT */ /* DIVT */
REQUIRE_FEN;
gen_divt(ctx, ra, rb, rc, fn11); gen_divt(ctx, ra, rb, rc, fn11);
break; break;
case 0x24: case 0x24:
/* CMPTUN */ /* CMPTUN */
REQUIRE_FEN;
gen_cmptun(ctx, ra, rb, rc, fn11); gen_cmptun(ctx, ra, rb, rc, fn11);
break; break;
case 0x25: case 0x25:
/* CMPTEQ */ /* CMPTEQ */
REQUIRE_FEN;
gen_cmpteq(ctx, ra, rb, rc, fn11); gen_cmpteq(ctx, ra, rb, rc, fn11);
break; break;
case 0x26: case 0x26:
/* CMPTLT */ /* CMPTLT */
REQUIRE_FEN;
gen_cmptlt(ctx, ra, rb, rc, fn11); gen_cmptlt(ctx, ra, rb, rc, fn11);
break; break;
case 0x27: case 0x27:
/* CMPTLE */ /* CMPTLE */
REQUIRE_FEN;
gen_cmptle(ctx, ra, rb, rc, fn11); gen_cmptle(ctx, ra, rb, rc, fn11);
break; break;
case 0x2C: case 0x2C:
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
if (fn11 == 0x2AC || fn11 == 0x6AC) { if (fn11 == 0x2AC || fn11 == 0x6AC) {
/* CVTST */ /* CVTST */
gen_cvtst(ctx, rb, rc, fn11); gen_cvtst(ctx, rb, rc, fn11);
@ -2262,16 +2304,19 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x2F: case 0x2F:
/* CVTTQ */ /* CVTTQ */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvttq(ctx, rb, rc, fn11); gen_cvttq(ctx, rb, rc, fn11);
break; break;
case 0x3C: case 0x3C:
/* CVTQS */ /* CVTQS */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvtqs(ctx, rb, rc, fn11); gen_cvtqs(ctx, rb, rc, fn11);
break; break;
case 0x3E: case 0x3E:
/* CVTQT */ /* CVTQT */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
gen_cvtqt(ctx, rb, rc, fn11); gen_cvtqt(ctx, rb, rc, fn11);
break; break;
default: default:
@ -2284,12 +2329,14 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x010: case 0x010:
/* CVTLQ */ /* CVTLQ */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_cvtlq(vc, vb); gen_cvtlq(vc, vb);
break; break;
case 0x020: case 0x020:
/* CPYS */ /* CPYS */
REQUIRE_FEN;
if (rc == 31) { if (rc == 31) {
/* Special case CPYS as FNOP. */ /* Special case CPYS as FNOP. */
} else { } else {
@ -2306,6 +2353,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x021: case 0x021:
/* CPYSN */ /* CPYSN */
REQUIRE_FEN;
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
@ -2313,6 +2361,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x022: case 0x022:
/* CPYSE */ /* CPYSE */
REQUIRE_FEN;
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
@ -2320,6 +2369,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x024: case 0x024:
/* MT_FPCR */ /* MT_FPCR */
REQUIRE_FEN;
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
gen_helper_store_fpcr(cpu_env, va); gen_helper_store_fpcr(cpu_env, va);
if (ctx->tb_rm == QUAL_RM_D) { if (ctx->tb_rm == QUAL_RM_D) {
@ -2330,37 +2380,45 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x025: case 0x025:
/* MF_FPCR */ /* MF_FPCR */
REQUIRE_FEN;
va = dest_fpr(ctx, ra); va = dest_fpr(ctx, ra);
gen_helper_load_fpcr(va, cpu_env); gen_helper_load_fpcr(va, cpu_env);
break; break;
case 0x02A: case 0x02A:
/* FCMOVEQ */ /* FCMOVEQ */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc); gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc);
break; break;
case 0x02B: case 0x02B:
/* FCMOVNE */ /* FCMOVNE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc); gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc);
break; break;
case 0x02C: case 0x02C:
/* FCMOVLT */ /* FCMOVLT */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc); gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc);
break; break;
case 0x02D: case 0x02D:
/* FCMOVGE */ /* FCMOVGE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc); gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc);
break; break;
case 0x02E: case 0x02E:
/* FCMOVLE */ /* FCMOVLE */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc); gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc);
break; break;
case 0x02F: case 0x02F:
/* FCMOVGT */ /* FCMOVGT */
REQUIRE_FEN;
gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc); gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc);
break; break;
case 0x030: /* CVTQL */ case 0x030: /* CVTQL */
case 0x130: /* CVTQL/V */ case 0x130: /* CVTQL/V */
case 0x530: /* CVTQL/SV */ case 0x530: /* CVTQL/SV */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_FEN;
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb); vb = load_fpr(ctx, rb);
gen_helper_cvtql(vc, cpu_env, vb); gen_helper_cvtql(vc, cpu_env, vb);
@ -2793,34 +2851,42 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
#endif #endif
case 0x20: case 0x20:
/* LDF */ /* LDF */
REQUIRE_FEN;
gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
break; break;
case 0x21: case 0x21:
/* LDG */ /* LDG */
REQUIRE_FEN;
gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
break; break;
case 0x22: case 0x22:
/* LDS */ /* LDS */
REQUIRE_FEN;
gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
break; break;
case 0x23: case 0x23:
/* LDT */ /* LDT */
REQUIRE_FEN;
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
break; break;
case 0x24: case 0x24:
/* STF */ /* STF */
REQUIRE_FEN;
gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);
break; break;
case 0x25: case 0x25:
/* STG */ /* STG */
REQUIRE_FEN;
gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);
break; break;
case 0x26: case 0x26:
/* STS */ /* STS */
REQUIRE_FEN;
gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);
break; break;
case 0x27: case 0x27:
/* STT */ /* STT */
REQUIRE_FEN;
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);
break; break;
case 0x28: case 0x28:
@ -2862,12 +2928,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
ret = gen_bdirect(ctx, ra, disp21); ret = gen_bdirect(ctx, ra, disp21);
break; break;
case 0x31: /* FBEQ */ case 0x31: /* FBEQ */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21);
break; break;
case 0x32: /* FBLT */ case 0x32: /* FBLT */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21);
break; break;
case 0x33: /* FBLE */ case 0x33: /* FBLE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21);
break; break;
case 0x34: case 0x34:
@ -2875,12 +2944,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
ret = gen_bdirect(ctx, ra, disp21); ret = gen_bdirect(ctx, ra, disp21);
break; break;
case 0x35: /* FBNE */ case 0x35: /* FBNE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21);
break; break;
case 0x36: /* FBGE */ case 0x36: /* FBGE */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21);
break; break;
case 0x37: /* FBGT */ case 0x37: /* FBGT */
REQUIRE_FEN;
ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21); ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21);
break; break;
case 0x38: case 0x38:
@ -2918,6 +2990,9 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
invalid_opc: invalid_opc:
ret = gen_invalid(ctx); ret = gen_invalid(ctx);
break; break;
raise_fen:
ret = gen_excp(ctx, EXCP_FEN, 0);
break;
} }
return ret; return ret;