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target-ppc: add instruction flags for Book I 2.05 

.. and enable it on POWER7 CPU.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Aurelien Jarno 2013-04-20 08:56:15 +00:00 committed by Alexander Graf
parent 88770fec6c
commit 9c2627b09d
2 changed files with 4 additions and 2 deletions
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4
target-ppc/cpu.h
View File

@ -1870,8 +1870,10 @@ enum {
PPC2_PRCNTL = 0x0000000000000008ULL, PPC2_PRCNTL = 0x0000000000000008ULL,
/* Byte-reversed, indexed, double-word load and store */ /* Byte-reversed, indexed, double-word load and store */
PPC2_DBRX = 0x0000000000000010ULL, PPC2_DBRX = 0x0000000000000010ULL,
/* Book I 2.05 PowerPC specification */
PPC2_ISA205 = 0x0000000000000020ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX) #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
}; };
/*****************************************************************************/ /*****************************************************************************/

2
target-ppc/translate_init.c
View File

@ -7042,7 +7042,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC | PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI | PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD; PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
pcc->msr_mask = 0x800000000204FF36ULL; pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06; pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)