mirror of https://github.com/xemu-project/xemu.git
target/arm: fix stage 2 page-walks in 32-bit emulation
Using a target unsigned long would limit the Input Address to a LPAE page-walk to 32 bits on AArch32 and 64 bits on AArch64. This is okay for stage 1 or on AArch64, but it is insufficient for stage 2 on AArch32. In that later case, the Input Address can have up to 40 bits. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201118150414.18360-1-remi@remlab.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -40,7 +40,7 @@
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#ifndef CONFIG_USER_ONLY
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static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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@ -10988,7 +10988,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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* @fi: set to fault info if the translation fails
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* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
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*/
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static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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