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target/mips: Document Loongson-3A CPU definitions 

Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1, "target/mips: Add Loongson-3 CPU definition").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-08-13 12:37:12 +02:00
parent bf7720024c
commit 98d207cf9c
1 changed files with 2 additions and 2 deletions
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4
target/mips/cpu-defs.c.inc
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@ -805,7 +805,7 @@ const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{ {
.name = "Loongson-3A1000", .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
.CP0_PRid = 0x6305, .CP0_PRid = 0x6305,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
@ -835,7 +835,7 @@ const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000, .mmu_type = MMU_TYPE_R4000,
}, },
{ {
.name = "Loongson-3A4000", /* GS464V-based */ .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
.CP0_PRid = 0x14C000, .CP0_PRid = 0x14C000,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |