From 984eda58f20763ffb56b7aff34ad60bdeb118eb1 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 21 Jun 2023 21:09:38 +1000 Subject: [PATCH] target/ppc: Fix sc instruction handling of LEV field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The top bits of the LEV field of the sc instruction are to be treated as as a reserved field rather than a reserved value, meaning LEV is effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be a hypercall, for example. This changes the instruction execution to just set lev from the low bit of the field. Processors which don't support the LEV field will continue to ignore it. ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall instruction. TCG does not support Ultravisor, so don't worry about that bit. Suggested-by: "Harsh Prateek Bora" Signed-off-by: Nicholas Piggin Reviewed-by: Harsh Prateek Bora Signed-off-by: Cédric Le Goater --- target/ppc/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1ade063616..8f74a864e4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4429,7 +4429,12 @@ static void gen_sc(DisasContext *ctx) { uint32_t lev; - lev = (ctx->opcode >> 5) & 0x7F; + /* + * LEV is a 7-bit field, but the top 6 bits are treated as a reserved + * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is + * for Ultravisor which TCG does not support, so just ignore the top 6. + */ + lev = (ctx->opcode >> 5) & 0x1; gen_exception_err(ctx, POWERPC_SYSCALL, lev); }