mirror of https://github.com/xemu-project/xemu.git
linux-user/host/riscv: Populate host_signal.h
Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
b12161120a
commit
97be8c6a95
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@ -137,64 +137,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
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}
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}
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}
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}
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/*
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* 'pc' is the host PC at which the exception was raised.
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* 'address' is the effective address of the memory exception.
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* 'is_write' is 1 if a write caused the exception and otherwise 0.
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* 'old_set' is the signal set which should be restored.
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*/
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static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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int is_write, sigset_t *old_set)
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{
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CPUState *cpu = current_cpu;
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CPUClass *cc;
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unsigned long host_addr = (unsigned long)info->si_addr;
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MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
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abi_ptr guest_addr;
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/* For synchronous signals we expect to be coming from the vCPU
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* thread (so current_cpu should be valid) and either from running
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* code or during translation which can fault as we cross pages.
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*
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* If neither is true then something has gone wrong and we should
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* abort rather than try and restart the vCPU execution.
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*/
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if (!cpu || !cpu->running) {
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printf("qemu:%s received signal outside vCPU context @ pc=0x%"
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PRIxPTR "\n", __func__, pc);
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abort();
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}
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, host_addr, is_write, *(unsigned long *)old_set);
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#endif
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/* Convert forcefully to guest address space, invalid addresses
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are still valid segv ones */
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guest_addr = h2g_nocheck(host_addr);
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/* XXX: locking issue */
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if (is_write &&
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info->si_signo == SIGSEGV &&
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info->si_code == SEGV_ACCERR &&
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h2g_valid(host_addr) &&
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handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
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return 1;
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}
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/*
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* There is no way the target can handle this other than raising
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* an exception. Undo signal and retaddr state prior to longjmp.
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*/
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sigprocmask(SIG_SETMASK, old_set, NULL);
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cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
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MMU_USER_IDX, false, pc);
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g_assert_not_reached();
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}
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static int probe_access_internal(CPUArchState *env, target_ulong addr,
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static int probe_access_internal(CPUArchState *env, target_ulong addr,
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int fault_size, MMUAccessType access_type,
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int fault_size, MMUAccessType access_type,
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bool nonfault, uintptr_t ra)
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bool nonfault, uintptr_t ra)
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@ -253,82 +195,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
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return size ? g2h(env_cpu(env), addr) : NULL;
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return size ? g2h(env_cpu(env), addr) : NULL;
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}
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}
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#if defined(__riscv)
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int cpu_signal_handler(int host_signum, void *pinfo,
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void *puc)
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{
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siginfo_t *info = pinfo;
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ucontext_t *uc = puc;
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greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
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uint32_t insn = *(uint32_t *)pc;
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int is_write = 0;
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/* Detect store by reading the instruction at the program
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counter. Note: we currently only generate 32-bit
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instructions so we thus only detect 32-bit stores */
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switch (((insn >> 0) & 0b11)) {
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case 3:
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switch (((insn >> 2) & 0b11111)) {
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case 8:
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switch (((insn >> 12) & 0b111)) {
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case 0: /* sb */
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case 1: /* sh */
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case 2: /* sw */
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case 3: /* sd */
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case 4: /* sq */
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is_write = 1;
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break;
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default:
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break;
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}
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break;
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case 9:
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switch (((insn >> 12) & 0b111)) {
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case 2: /* fsw */
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case 3: /* fsd */
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case 4: /* fsq */
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is_write = 1;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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/* Check for compressed instructions */
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switch (((insn >> 13) & 0b111)) {
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case 7:
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switch (insn & 0b11) {
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case 0: /*c.sd */
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case 2: /* c.sdsp */
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is_write = 1;
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break;
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default:
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break;
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}
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break;
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case 6:
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switch (insn & 0b11) {
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case 0: /* c.sw */
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case 3: /* c.swsp */
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is_write = 1;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
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}
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#endif
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/* The softmmu versions of these helpers are in cputlb.c. */
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/* The softmmu versions of these helpers are in cputlb.c. */
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/*
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/*
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@ -1 +1,85 @@
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#define HOST_SIGNAL_PLACEHOLDER
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/*
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* host-signal.h: signal info dependent on the host architecture
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2021 Linaro Limited
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef RISCV_HOST_SIGNAL_H
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#define RISCV_HOST_SIGNAL_H
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static inline uintptr_t host_signal_pc(ucontext_t *uc)
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{
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return uc->uc_mcontext.__gregs[REG_PC];
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}
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static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
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{
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uint32_t insn = *(uint32_t *)host_signal_pc(uc);
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/*
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* Detect store by reading the instruction at the program
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* counter. Note: we currently only generate 32-bit
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* instructions so we thus only detect 32-bit stores
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*/
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switch (((insn >> 0) & 0b11)) {
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case 3:
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switch (((insn >> 2) & 0b11111)) {
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case 8:
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switch (((insn >> 12) & 0b111)) {
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case 0: /* sb */
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case 1: /* sh */
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case 2: /* sw */
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case 3: /* sd */
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case 4: /* sq */
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return true;
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default:
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break;
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}
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break;
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case 9:
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switch (((insn >> 12) & 0b111)) {
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case 2: /* fsw */
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case 3: /* fsd */
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case 4: /* fsq */
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return true;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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/* Check for compressed instructions */
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switch (((insn >> 13) & 0b111)) {
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case 7:
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switch (insn & 0b11) {
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case 0: /*c.sd */
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case 2: /* c.sdsp */
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return true;
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default:
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break;
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}
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break;
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case 6:
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switch (insn & 0b11) {
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case 0: /* c.sw */
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case 3: /* c.swsp */
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return true;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return false;
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}
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#endif
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