mirror of https://github.com/xemu-project/xemu.git
target-i386: Remove gen_op_movl_T0_0
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
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}
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}
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static inline void gen_op_movl_T0_0(void)
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{
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tcg_gen_movi_tl(cpu_T[0], 0);
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}
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static inline void gen_op_movl_T0_im(int32_t val)
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{
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tcg_gen_movi_tl(cpu_T[0], val);
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@ -1257,7 +1252,7 @@ static inline void gen_ins(DisasContext *s, int ot)
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gen_string_movl_A0_EDI(s);
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/* Note: we must do this dummy write first to be restartable in
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case of page fault. */
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
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tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
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@ -3271,7 +3266,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_lea_modrm(env, s, modrm);
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gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
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@ -3286,7 +3281,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_lea_modrm(env, s, modrm);
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gen_ldq_env_A0(s, offsetof(CPUX86State,
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xmm_regs[reg].XMM_Q(0)));
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
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} else {
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@ -3507,13 +3502,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (is_xmm) {
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gen_op_movl_T0_im(val);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
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op1_offset = offsetof(CPUX86State,xmm_t0);
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} else {
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gen_op_movl_T0_im(val);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
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op1_offset = offsetof(CPUX86State,mmx_t0);
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}
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@ -4716,7 +4711,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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xor_zero:
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/* xor reg, reg optimisation */
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set_cc_op(s, CC_OP_CLR);
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gen_op_movl_T0_0();
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tcg_gen_movi_tl(cpu_T[0], 0);
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gen_op_mov_reg_T0(ot, reg);
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break;
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} else {
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