mirror of https://github.com/xemu-project/xemu.git
target/arm: Move combine_cacheattrs and subroutines to ptw.c
There are a handful of helpers for combine_cacheattrs that we can move at the same time as the main entry point. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
4c74ab157b
commit
966f4bb7d8
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@ -10977,36 +10977,6 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
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}
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return true;
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}
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/* Translate from the 4-bit stage 2 representation of
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* memory attributes (without cache-allocation hints) to
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* the 8-bit representation of the stage 1 MAIR registers
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* (which includes allocation hints).
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*
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* ref: shared/translation/attrs/S2AttrDecode()
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* .../S2ConvertAttrsHints()
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*/
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static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
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{
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uint8_t hiattr = extract32(s2attrs, 2, 2);
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uint8_t loattr = extract32(s2attrs, 0, 2);
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uint8_t hihint = 0, lohint = 0;
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if (hiattr != 0) { /* normal memory */
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if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
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hiattr = loattr = 1; /* non-cacheable */
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} else {
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if (hiattr != 1) { /* Write-through or write-back */
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hihint = 3; /* RW allocate */
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}
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if (loattr != 1) { /* Write-through or write-back */
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lohint = 3; /* RW allocate */
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}
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}
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}
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return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
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}
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#endif /* !CONFIG_USER_ONLY */
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/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
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@ -11653,194 +11623,6 @@ do_fault:
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return true;
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}
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/* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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*
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* NB: only stage 1 includes allocation hints (RW bits), leading to
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* some asymmetry.
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*/
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static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
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{
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if (s1 == 4 || s2 == 4) {
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/* non-cacheable has precedence */
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return 4;
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} else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
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/* stage 1 write-through takes precedence */
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return s1;
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} else if (extract32(s2, 2, 2) == 2) {
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/* stage 2 write-through takes precedence, but the allocation hint
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* is still taken from stage 1
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*/
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return (2 << 2) | extract32(s1, 0, 2);
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} else { /* write-back */
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return s1;
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}
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_nofwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
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s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2_mair_attrs, 0, 4);
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s1hi = extract32(s1.attrs, 4, 4);
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s2hi = extract32(s2_mair_attrs, 4, 4);
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/* Combine memory type and cacheability attributes */
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if (s1hi == 0 || s2hi == 0) {
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/* Device has precedence over normal */
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if (s1lo == 0 || s2lo == 0) {
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/* nGnRnE has precedence over anything */
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ret_attrs = 0;
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} else if (s1lo == 4 || s2lo == 4) {
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/* non-Reordering has precedence over Reordering */
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ret_attrs = 4; /* nGnRE */
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} else if (s1lo == 8 || s2lo == 8) {
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/* non-Gathering has precedence over Gathering */
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ret_attrs = 8; /* nGRE */
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} else {
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ret_attrs = 0xc; /* GRE */
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}
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} else { /* Normal memory */
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/* Outer/inner cacheability combine independently */
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ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
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| combine_cacheattr_nibble(s1lo, s2lo);
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}
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return ret_attrs;
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}
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static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
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{
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/*
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* Given the 4 bits specifying the outer or inner cacheability
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* in MAIR format, return a value specifying Normal Write-Back,
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* with the allocation and transient hints taken from the input
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* if the input specified some kind of cacheable attribute.
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*/
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if (attr == 0 || attr == 4) {
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/*
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* 0 == an UNPREDICTABLE encoding
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* 4 == Non-cacheable
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* Either way, force Write-Back RW allocate non-transient
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*/
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return 0xf;
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}
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/* Change WriteThrough to WriteBack, keep allocation and transient hints */
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return attr | 4;
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_fwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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switch (s2.attrs) {
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case 7:
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/* Use stage 1 attributes */
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return s1.attrs;
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case 6:
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/*
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* Force Normal Write-Back. Note that if S1 is Normal cacheable
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* then we take the allocation hints from it; otherwise it is
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* RW allocate, non-transient.
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*/
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if ((s1.attrs & 0xf0) == 0) {
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/* S1 is Device */
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return 0xff;
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}
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/* Need to check the Inner and Outer nibbles separately */
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return force_cacheattr_nibble_wb(s1.attrs & 0xf) |
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force_cacheattr_nibble_wb(s1.attrs >> 4) << 4;
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case 5:
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/* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
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if ((s1.attrs & 0xf0) == 0) {
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return s1.attrs;
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}
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return 0x44;
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case 0 ... 3:
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/* Force Device, of subtype specified by S2 */
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return s2.attrs << 2;
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default:
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/*
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* RESERVED values (including RES0 descriptor bit [5] being nonzero);
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* arbitrarily force Device.
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*/
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return 0;
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}
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}
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/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
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* and CombineS1S2Desc()
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*
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* @env: CPUARMState
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* @s1: Attributes from stage 1 walk
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* @s2: Attributes from stage 2 walk
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*/
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ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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ARMCacheAttrs ret;
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bool tagged = false;
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assert(s2.is_s2_format && !s1.is_s2_format);
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ret.is_s2_format = false;
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if (s1.attrs == 0xf0) {
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tagged = true;
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s1.attrs = 0xff;
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}
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/* Combine shareability attributes (table D4-43) */
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if (s1.shareability == 2 || s2.shareability == 2) {
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/* if either are outer-shareable, the result is outer-shareable */
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ret.shareability = 2;
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} else if (s1.shareability == 3 || s2.shareability == 3) {
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/* if either are inner-shareable, the result is inner-shareable */
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ret.shareability = 3;
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} else {
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/* both non-shareable */
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ret.shareability = 0;
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}
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/* Combine memory type and cacheability attributes */
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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ret.attrs = combined_attrs_fwb(env, s1, s2);
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} else {
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ret.attrs = combined_attrs_nofwb(env, s1, s2);
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}
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/*
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* Any location for which the resultant memory type is any
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* type of Device memory is always treated as Outer Shareable.
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* Any location for which the resultant memory type is Normal
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* Inner Non-cacheable, Outer Non-cacheable is always treated
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* as Outer Shareable.
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* TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
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*/
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if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) {
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ret.shareability = 2;
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}
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/* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
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if (tagged && ret.attrs == 0xff) {
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ret.attrs = 0xf0;
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}
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return ret;
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}
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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MemTxAttrs *attrs)
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{
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221
target/arm/ptw.c
221
target/arm/ptw.c
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@ -1008,6 +1008,227 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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return ret;
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}
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/*
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* Translate from the 4-bit stage 2 representation of
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* memory attributes (without cache-allocation hints) to
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* the 8-bit representation of the stage 1 MAIR registers
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* (which includes allocation hints).
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*
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* ref: shared/translation/attrs/S2AttrDecode()
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* .../S2ConvertAttrsHints()
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*/
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static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
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{
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uint8_t hiattr = extract32(s2attrs, 2, 2);
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uint8_t loattr = extract32(s2attrs, 0, 2);
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uint8_t hihint = 0, lohint = 0;
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if (hiattr != 0) { /* normal memory */
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if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
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hiattr = loattr = 1; /* non-cacheable */
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} else {
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if (hiattr != 1) { /* Write-through or write-back */
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hihint = 3; /* RW allocate */
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}
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if (loattr != 1) { /* Write-through or write-back */
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lohint = 3; /* RW allocate */
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}
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}
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}
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return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
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}
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/*
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* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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*
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* NB: only stage 1 includes allocation hints (RW bits), leading to
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* some asymmetry.
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*/
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static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
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{
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if (s1 == 4 || s2 == 4) {
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/* non-cacheable has precedence */
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return 4;
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} else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
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/* stage 1 write-through takes precedence */
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return s1;
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} else if (extract32(s2, 2, 2) == 2) {
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/* stage 2 write-through takes precedence, but the allocation hint
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* is still taken from stage 1
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*/
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return (2 << 2) | extract32(s1, 0, 2);
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} else { /* write-back */
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return s1;
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}
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_nofwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
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s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2_mair_attrs, 0, 4);
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s1hi = extract32(s1.attrs, 4, 4);
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s2hi = extract32(s2_mair_attrs, 4, 4);
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/* Combine memory type and cacheability attributes */
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if (s1hi == 0 || s2hi == 0) {
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/* Device has precedence over normal */
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if (s1lo == 0 || s2lo == 0) {
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/* nGnRnE has precedence over anything */
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ret_attrs = 0;
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} else if (s1lo == 4 || s2lo == 4) {
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/* non-Reordering has precedence over Reordering */
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ret_attrs = 4; /* nGnRE */
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} else if (s1lo == 8 || s2lo == 8) {
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/* non-Gathering has precedence over Gathering */
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ret_attrs = 8; /* nGRE */
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} else {
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ret_attrs = 0xc; /* GRE */
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}
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} else { /* Normal memory */
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/* Outer/inner cacheability combine independently */
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ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
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| combine_cacheattr_nibble(s1lo, s2lo);
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}
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return ret_attrs;
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}
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static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
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{
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/*
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* Given the 4 bits specifying the outer or inner cacheability
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* in MAIR format, return a value specifying Normal Write-Back,
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* with the allocation and transient hints taken from the input
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* if the input specified some kind of cacheable attribute.
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*/
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if (attr == 0 || attr == 4) {
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/*
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* 0 == an UNPREDICTABLE encoding
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* 4 == Non-cacheable
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* Either way, force Write-Back RW allocate non-transient
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*/
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return 0xf;
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}
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/* Change WriteThrough to WriteBack, keep allocation and transient hints */
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return attr | 4;
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_fwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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switch (s2.attrs) {
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case 7:
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/* Use stage 1 attributes */
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return s1.attrs;
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case 6:
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/*
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* Force Normal Write-Back. Note that if S1 is Normal cacheable
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* then we take the allocation hints from it; otherwise it is
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* RW allocate, non-transient.
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*/
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if ((s1.attrs & 0xf0) == 0) {
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/* S1 is Device */
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return 0xff;
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}
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/* Need to check the Inner and Outer nibbles separately */
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return force_cacheattr_nibble_wb(s1.attrs & 0xf) |
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force_cacheattr_nibble_wb(s1.attrs >> 4) << 4;
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case 5:
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/* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
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if ((s1.attrs & 0xf0) == 0) {
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return s1.attrs;
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}
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return 0x44;
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case 0 ... 3:
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/* Force Device, of subtype specified by S2 */
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return s2.attrs << 2;
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default:
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/*
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* RESERVED values (including RES0 descriptor bit [5] being nonzero);
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* arbitrarily force Device.
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*/
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return 0;
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}
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}
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/*
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* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
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* and CombineS1S2Desc()
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*
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* @env: CPUARMState
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* @s1: Attributes from stage 1 walk
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* @s2: Attributes from stage 2 walk
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*/
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static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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ARMCacheAttrs ret;
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bool tagged = false;
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assert(s2.is_s2_format && !s1.is_s2_format);
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ret.is_s2_format = false;
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if (s1.attrs == 0xf0) {
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tagged = true;
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s1.attrs = 0xff;
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}
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/* Combine shareability attributes (table D4-43) */
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if (s1.shareability == 2 || s2.shareability == 2) {
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/* if either are outer-shareable, the result is outer-shareable */
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ret.shareability = 2;
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} else if (s1.shareability == 3 || s2.shareability == 3) {
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/* if either are inner-shareable, the result is inner-shareable */
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ret.shareability = 3;
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} else {
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/* both non-shareable */
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ret.shareability = 0;
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}
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/* Combine memory type and cacheability attributes */
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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ret.attrs = combined_attrs_fwb(env, s1, s2);
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} else {
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ret.attrs = combined_attrs_nofwb(env, s1, s2);
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}
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/*
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* Any location for which the resultant memory type is any
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* type of Device memory is always treated as Outer Shareable.
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* Any location for which the resultant memory type is Normal
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* Inner Non-cacheable, Outer Non-cacheable is always treated
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* as Outer Shareable.
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* TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
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||||
*/
|
||||
if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) {
|
||||
ret.shareability = 2;
|
||||
}
|
||||
|
||||
/* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
|
||||
if (tagged && ret.attrs == 0xff) {
|
||||
ret.attrs = 0xf0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_phys_addr - get the physical address for this virtual address
|
||||
*
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx);
|
|||
bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx);
|
||||
uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn);
|
||||
|
||||
ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
|
||||
ARMCacheAttrs s1, ARMCacheAttrs s2);
|
||||
|
||||
int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
|
||||
int ap, int domain_prot);
|
||||
int simple_ap_to_rw_prot_is_user(int ap, bool is_user);
|
||||
|
|
|
|||
Loading…
Reference in New Issue