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aspeed: Add a DRAM memory region at the SoC level 

Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-4-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2019-11-19 15:11:57 +01:00 committed by Peter Maydell
parent aab90b1cac
commit 95b56e173e
3 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/arm/aspeed_ast2600.c
View File

@ -158,8 +158,6 @@ static void aspeed_soc_ast2600_init(Object *obj)
typename); typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
&error_abort); &error_abort);
object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
&error_abort);
for (i = 0; i < sc->spis_num; i++) { for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
@ -362,6 +360,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
} }
/* FMC, The number of CS is set at the board level */ /* FMC, The number of CS is set at the board level */
object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
"sdram-base", &err); "sdram-base", &err);
if (err) { if (err) {

9
hw/arm/aspeed_soc.c
View File

@ -175,8 +175,6 @@ static void aspeed_soc_init(Object *obj)
typename); typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
&error_abort); &error_abort);
object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
&error_abort);
for (i = 0; i < sc->spis_num; i++) { for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
@ -323,6 +321,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_I2C)); aspeed_soc_get_irq(s, ASPEED_I2C));
/* FMC, The number of CS is set at the board level */ /* FMC, The number of CS is set at the board level */
object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
"sdram-base", &err); "sdram-base", &err);
if (err) { if (err) {
@ -429,6 +432,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
} }
static Property aspeed_soc_properties[] = { static Property aspeed_soc_properties[] = {
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

1
include/hw/arm/aspeed_soc.h
View File

@ -40,6 +40,7 @@ typedef struct AspeedSoCState {
ARMCPU cpu[ASPEED_CPUS_NUM]; ARMCPU cpu[ASPEED_CPUS_NUM];
uint32_t num_cpus; uint32_t num_cpus;
A15MPPrivState a7mpcore; A15MPPrivState a7mpcore;
MemoryRegion *dram_mr;
MemoryRegion sram; MemoryRegion sram;
AspeedVICState vic; AspeedVICState vic;
AspeedRtcState rtc; AspeedRtcState rtc;