mirror of https://github.com/xemu-project/xemu.git
sparc64: implement basic IOMMU/interrupt handling
Also add reset control. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
a4d5f62ceb
commit
95819af015
162
hw/apb_pci.c
162
hw/apb_pci.c
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@ -50,23 +50,74 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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#define PBM_PCI_IMR_MASK 0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR (1 << 31)
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#define SOFT_POR (1 << 30)
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#define SOFT_XIR (1 << 29)
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#define BTN_POR (1 << 28)
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#define BTN_XIR (1 << 27)
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#define RESET_MASK 0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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typedef struct APBState {
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SysBusDevice busdev;
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PCIHostState host_state;
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uint32_t iommu[4];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq pci_irqs[32];
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uint32_t reset_control;
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} APBState;
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static unsigned int nr_resets;
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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//PCIBus *s = opaque;
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APBState *s = opaque;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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s->iommu[(addr & 0xf) >> 2] = val;
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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s->pci_control[(addr & 0x3f) >> 2] = val;
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val &= RESET_MASK;
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control |= val & RESET_WMASK;
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if (val & SOFT_POR) {
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nr_resets = 0;
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qemu_system_reset_request();
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} else if (val & SOFT_XIR) {
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qemu_system_reset_request();
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}
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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break;
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}
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@ -75,20 +126,48 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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static uint32_t apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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//PCIBus *s = opaque;
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APBState *s = opaque;
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uint32_t val;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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val = 0;
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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val = s->iommu[(addr & 0xf) >> 2];
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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val = 0;
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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val = s->pci_irq_map[(addr & 0x3f) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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val = s->pci_control[(addr & 0x3f) >> 2];
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val = s->reset_control;
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} else {
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val = 0;
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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val = 0;
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break;
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}
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
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return val;
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}
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@ -252,10 +331,18 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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APBState *s = opaque;
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/* PCI IRQ map onto the first 32 INO. */
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qemu_set_irq(pic[irq_num], level);
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if (irq_num < 32) {
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->pci_irqs[irq_num], level);
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->pci_irqs[irq_num]);
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}
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}
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}
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static void apb_pci_bridge_init(PCIBus *b)
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@ -284,6 +371,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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DeviceState *dev;
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SysBusDevice *s;
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APBState *d;
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unsigned int i;
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, "pbm");
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@ -299,10 +387,14 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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sysbus_mmio_map(s, 3, mem_base);
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d = FROM_SYSBUS(APBState, s);
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_apb_set_irq, pci_pbm_map_irq, pic,
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pci_apb_set_irq, pci_pbm_map_irq, d,
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0, 32);
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pci_bus_set_mem_base(d->host_state.bus, mem_base);
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for (i = 0; i < 32; i++) {
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sysbus_connect_irq(s, i, pic[i]);
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}
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pci_create_simple(d->host_state.bus, 0, "pbm");
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/* APB secondary busses */
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*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
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@ -320,13 +412,35 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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return d->host_state.bus;
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}
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static void pci_pbm_reset(DeviceState *d)
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{
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unsigned int i;
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APBState *s = container_of(d, APBState, busdev.qdev);
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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if (nr_resets++ == 0) {
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/* Power on reset */
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s->reset_control = POR;
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}
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}
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static int pci_pbm_init_device(SysBusDevice *dev)
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{
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APBState *s;
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int pci_mem_data, apb_config, pci_ioport, pci_config;
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unsigned int i;
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s = FROM_SYSBUS(APBState, dev);
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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}
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for (i = 0; i < 32; i++) {
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sysbus_init_irq(dev, &s->pci_irqs[i]);
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}
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/* apb_config */
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apb_config = cpu_register_io_memory(apb_config_read,
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apb_config_write, s);
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@ -368,9 +482,15 @@ static PCIDeviceInfo pbm_pci_host_info = {
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.header_type = PCI_HEADER_TYPE_BRIDGE,
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};
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static SysBusDeviceInfo pbm_host_info = {
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.qdev.name = "pbm",
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.qdev.size = sizeof(APBState),
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.qdev.reset = pci_pbm_reset,
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.init = pci_pbm_init_device,
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};
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static void pbm_register_devices(void)
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{
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sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
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sysbus_register_withprop(&pbm_host_info);
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pci_qdev_register(&pbm_pci_host_info);
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}
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