mirror of https://github.com/xemu-project/xemu.git
target-arm queue:
* Don't report Statistical Profiling Extension in ID registers * virt ACPI tables: Present the GICR structure properly for GICv4 * Fix some typos in documentation * tests/unit: fix a -Wformat-truncation warning * cutils: Add missing dyld(3) include on macOS -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmL2PP4ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qLKD/964d9vRe9b1Upv5mTxM7+y JxgwvsgVe7HeWBTOIIHsP7y1F+5MduiDDf2BC5XBiwtkVNSeJB1J1QQWkas6baVr DiRPiP/D6gG3B9naujCWsI5QbnSlONeunE0R+gYfNK6J/Odidzu6DtNa4PZJ1tcP vmZA5eLSAjaCIVmzQYF/Ae7nSoFz/sVR+li+tLSb/ynC+3H+rCry4TrQ7HgGyhjO nz4hIOtiYdAqp6hklMeLl6yAPMwZrxCtq51LE+Oj90uh7xt3gs0d29Zlbdc/vQFw dSZM/Cm0X+TMV6HHjpKrHnoUH+o+yv/O1q7VFccC4UpLSj7jbB8o/fbCASsBV+Jg /Y87G9WjtS6EO5SEqnDTSw5cAEKAqpgzQe8HhEGFa3MymuzkrnBagj59TNa5t4hV +maoR2vRb8hnhYDtFsWDPbfhFSCP3MSHki6sP7IMFNQsaUxFDNu2mRn0TOtSx0NB n5a/JOby7AeYI5JWyAwQ2T5Hxgh8EeBrPsXDxyy1jA+t67nrlrqdYwyLL5564jU4 ESuMnuRTWjUnXaF9yhKbe6g1QdVV3OAC6jikzMuYLEHmKC/1MUJT1W4MECzjx1FM b0tQ2Q+0mfSfm5YrJqbAIdDg3Cie88pvl/i0POtFBiwoOhPRH6QBzd/b6q6B6zw6 MPV6QAwBfdQYxJId93shTQ== =/sV7 -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20220812' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Don't report Statistical Profiling Extension in ID registers * virt ACPI tables: Present the GICR structure properly for GICv4 * Fix some typos in documentation * tests/unit: fix a -Wformat-truncation warning * cutils: Add missing dyld(3) include on macOS # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmL2PP4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qLKD/964d9vRe9b1Upv5mTxM7+y # JxgwvsgVe7HeWBTOIIHsP7y1F+5MduiDDf2BC5XBiwtkVNSeJB1J1QQWkas6baVr # DiRPiP/D6gG3B9naujCWsI5QbnSlONeunE0R+gYfNK6J/Odidzu6DtNa4PZJ1tcP # vmZA5eLSAjaCIVmzQYF/Ae7nSoFz/sVR+li+tLSb/ynC+3H+rCry4TrQ7HgGyhjO # nz4hIOtiYdAqp6hklMeLl6yAPMwZrxCtq51LE+Oj90uh7xt3gs0d29Zlbdc/vQFw # dSZM/Cm0X+TMV6HHjpKrHnoUH+o+yv/O1q7VFccC4UpLSj7jbB8o/fbCASsBV+Jg # /Y87G9WjtS6EO5SEqnDTSw5cAEKAqpgzQe8HhEGFa3MymuzkrnBagj59TNa5t4hV # +maoR2vRb8hnhYDtFsWDPbfhFSCP3MSHki6sP7IMFNQsaUxFDNu2mRn0TOtSx0NB # n5a/JOby7AeYI5JWyAwQ2T5Hxgh8EeBrPsXDxyy1jA+t67nrlrqdYwyLL5564jU4 # ESuMnuRTWjUnXaF9yhKbe6g1QdVV3OAC6jikzMuYLEHmKC/1MUJT1W4MECzjx1FM # b0tQ2Q+0mfSfm5YrJqbAIdDg3Cie88pvl/i0POtFBiwoOhPRH6QBzd/b6q6B6zw6 # MPV6QAwBfdQYxJId93shTQ== # =/sV7 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 12 Aug 2022 04:43:58 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220812' of https://git.linaro.org/people/pmaydell/qemu-arm: cutils: Add missing dyld(3) include on macOS hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4 tests/unit: fix a -Wformat-truncation warning Fix some typos in documentation (most of them found by codespell) target/arm: Don't report Statistical Profiling Extension in ID registers Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
93f3dd6048
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@ -297,7 +297,7 @@ by using ``-machine graphics=off``.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64
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identifer that is not globally unique. If an EUI-64 identifer is required, the
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identifier that is not globally unique. If an EUI-64 identifier is required, the
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user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
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``-device nvme,use-intel-id=on|off`` (since 7.1)
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@ -108,7 +108,7 @@ Slot 0 contains a backend storage header that identifies the contents
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as ERST and also facilitates efficient access to the records.
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Depending upon the size of the backend storage, additional slots will
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be designated to be a part of the slot 0 header. For example, at 8KiB,
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the slot 0 header can accomodate 1021 records. Thus a storage size
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the slot 0 header can accommodate 1021 records. Thus a storage size
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of 8MiB (8KiB * 1024) requires an additional slot for use by the
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header. In this scenario, slot 0 and slot 1 form the backend storage
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header, and records can be stored starting at slot 2.
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@ -196,5 +196,5 @@ References
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[2] "Unified Extensible Firmware Interface Specification",
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version 2.1, October 2008.
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[3] "Windows Hardware Error Architecture", specfically
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[3] "Windows Hardware Error Architecture", specifically
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"Error Record Persistence Mechanism".
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@ -28,9 +28,9 @@ With the same software configuration as a hardware key,
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the guest OS can use all the functionalities of a secure key as if
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there was actually an hardware key plugged in.
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CanoKey QEMU provides much convenience for debuging:
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CanoKey QEMU provides much convenience for debugging:
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* libcanokey-qemu supports debuging output thus developers can
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* libcanokey-qemu supports debugging output thus developers can
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inspect what happens inside a secure key
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* CanoKey QEMU supports trace event thus event
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* QEMU USB stack supports pcap thus USB packet between the guest
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@ -102,8 +102,8 @@ and find CanoKey QEMU there:
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You may setup the key as guided in [6]_. The console for the key is at [7]_.
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Debuging
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========
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Debugging
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=========
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CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``,
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the latter of which resides in QEMU. The former provides core functionality
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@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW)
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A CFMW consists of a particular range of Host Physical Address space
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which is routed to particular CXL Host Bridges. At time of generic
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software initialization it will have a particularly interleaving
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configuration and associated Quality of Serice Throtling Group (QTG).
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configuration and associated Quality of Service Throttling Group (QTG).
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This information is available to system software, when making
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decisions about how to configure interleave across available CXL
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memory devices. It is provide as CFMW Structures (CFMWS) in
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@ -98,7 +98,7 @@ specification defined register interface called CXL Host Bridge
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Component Registers (CHBCR). The location of this CHBCR MMIO
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space is described to system software via a CXL Host Bridge
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Structure (CHBS) in the CEDT ACPI table. The actual interfaces
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are identical to those used for other parts of the CXL heirarchy
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are identical to those used for other parts of the CXL hierarchy
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as CXL Component Registers in PCI BARs.
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Interfaces provided include:
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@ -143,7 +143,7 @@ CXL Memory Devices - Type 3
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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CXL type 3 devices use a PCI class code and are intended to be supported
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by a generic operating system driver. They have HDM decoders
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though in these EP devices, the decoder is reponsible not for
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though in these EP devices, the decoder is responsible not for
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routing but for translation of the incoming host physical address (HPA)
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into a Device Physical Address (DPA).
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@ -209,7 +209,7 @@ Notes:
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ranges of the system physical address map. Each CFMW has
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particular interleave setup across the CXL Host Bridges (HB)
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CFMW0 provides uninterleaved access to HB0, CFW2 provides
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uninterleaved acess to HB1. CFW1 provides interleaved memory access
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uninterleaved access to HB1. CFW1 provides interleaved memory access
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across HB0 and HB1.
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(2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
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@ -282,7 +282,7 @@ Example topology involving a switch::
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---------------------------------------------------
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| Switch 0 USP as PCI 0d:00.0 |
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| USP has HDM decoder which direct traffic to |
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| appropiate downstream port |
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| appropriate downstream port |
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| Switch BUS appears as 0e |
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|x__________________________________________________|
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| | | |
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@ -366,7 +366,7 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave::
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Kernel Configuration Options
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----------------------------
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In Linux 5.18 the followings options are necessary to make use of
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In Linux 5.18 the following options are necessary to make use of
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OS management of CXL memory devices as described here.
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* CONFIG_CXL_BUS
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@ -732,7 +732,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
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PPI(VIRTUAL_PMU_IRQ) : 0;
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if (vms->gic_version == 2) {
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if (vms->gic_version == VIRT_GIC_VERSION_2) {
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physical_base_address = memmap[VIRT_GIC_CPU].base;
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gicv = memmap[VIRT_GIC_VCPU].base;
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gich = memmap[VIRT_GIC_HYP].base;
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@ -762,7 +762,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
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}
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if (vms->gic_version == 3) {
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if (vms->gic_version != VIRT_GIC_VERSION_2) {
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build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
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memmap[VIRT_GIC_REDIST].size);
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if (virt_gicv3_redist_region_count(vms) == 2) {
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@ -1933,6 +1933,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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}
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#endif
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if (tcg_enabled()) {
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/*
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* Don't report the Statistical Profiling Extension in the ID
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* registers, because TCG doesn't implement it yet (not even a
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* minimal stub version) and guests will fall over when they
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* try to access the non-existent system registers for it.
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*/
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cpu->isar.id_aa64dfr0 =
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FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
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}
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/* MPU can be configured out of a PMSA CPU either by setting has-mpu
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* to false or by setting pmsav7-dregion to 0.
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*/
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@ -447,9 +447,8 @@ static void test_visitor_in_list(TestInputVisitorData *data,
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g_assert(head != NULL);
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for (i = 0, item = head; item; item = item->next, i++) {
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char string[12];
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g_autofree char *string = g_strdup_printf("string%d", i);
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snprintf(string, sizeof(string), "string%d", i);
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g_assert_cmpstr(item->value->string, ==, string);
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g_assert_cmpint(item->value->integer, ==, 42 + i);
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}
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@ -39,6 +39,10 @@
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#include <kernel/image.h>
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#endif
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#ifdef __APPLE__
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#include <mach-o/dyld.h>
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#endif
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#ifdef G_OS_WIN32
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#include <pathcch.h>
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#include <wchar.h>
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@ -58,10 +58,6 @@
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#include <lwp.h>
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#endif
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#ifdef __APPLE__
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#include <mach-o/dyld.h>
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#endif
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#include "qemu/mmap-alloc.h"
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#ifdef CONFIG_DEBUG_STACK_USAGE
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