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target/riscv: Fix shift count overflow 

The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.

Signed-off-by: demin.han <demin.han@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
demin.han 2024-02-26 01:41:14 +08:00 committed by Alistair Francis
parent a506c4289d
commit 938dd05ea1
1 changed files with 2 additions and 3 deletions
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5
target/riscv/vector_helper.c
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@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
target_ulong reserved = s2 &
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
uint16_t vlen = cpu->cfg.vlenb << 3;
int8_t lmul;
if (vlmul & 4) {
@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
* vlenb >> (8 - 3 - lmul) >= sew
*/
if (vlmul == 4 ||
cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
vill = true;
}
}