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QOM device refactorings 

* Avoid TYPE_* in VMStateDescription name
 * Replace some DO_UPCAST()s and FROM_SYSBUS()s with QOM casts
 * Limit legacy SCSI command line handling to non-hotplugged devices
 * Replace some SysBusDeviceClass::init with DeviceClass::realize
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Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging

QOM device refactorings

* Avoid TYPE_* in VMStateDescription name
* Replace some DO_UPCAST()s and FROM_SYSBUS()s with QOM casts
* Limit legacy SCSI command line handling to non-hotplugged devices
* Replace some SysBusDeviceClass::init with DeviceClass::realize

# gpg: Signature made Mon 22 Jul 2013 06:31:42 PM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found

# By Hu Tao (26) and others
# Via Andreas Färber
* afaerber/tags/qom-devices-for-anthony: (55 commits)
  isa-bus: Drop isabus_bridge_init() since it does nothing
  ioapic: Use QOM realize for ioapic
  kvmvapic: Use QOM realize
  kvm/clock: Use QOM realize for kvmclock
  hpet: Use QOM realize for hpet
  scsi: Improve error propagation for scsi_bus_legacy_handle_cmdline()
  megasas: Legacy command line handling fix
  scsi/esp: Use QOM realize for scsi esp
  fw_cfg: Use QOM realize for fw_cfg
  ahci: Use QOM realize for ahci
  pflash_cfi02: Use QOM realize for pflash_cfi02
  pflash_cfi01: Use QOM realize for pflash_cfi01
  fdc: Improve error propagation for QOM realize
  fdc: Use QOM realize for fdc
  kvm/clock: QOM'ify some more
  hpet: QOM'ify some more
  scsi/esp: QOM'ify some more
  fwcfg: QOM'ify some more
  ahci: QOM'ify some more
  pflash-cfi02: QOM'ify some more
  ...
This commit is contained in:
Anthony Liguori 2013-07-23 10:56:55 -05:00
parent 3464700f6a 52785d9951
commit 931f0adf64
43 changed files with 858 additions and 563 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
hw/acpi/piix4.c
View File

@ -64,7 +64,9 @@ typedef struct CPUStatus {
} CPUStatus;
typedef struct PIIX4PMState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion io;
MemoryRegion io_gpe;
@ -96,6 +98,11 @@ typedef struct PIIX4PMState {
Notifier cpu_added_notifier;
} PIIX4PMState;
#define TYPE_PIIX4_PM "PIIX4_PM"
#define PIIX4_PM(obj) \
OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
PCIBus *bus, PIIX4PMState *s);
@ -130,11 +137,12 @@ static void pm_tmr_timer(ACPIREGS *ar)
static void apm_ctrl_changed(uint32_t val, void *arg)
{
PIIX4PMState *s = arg;
PCIDevice *d = PCI_DEVICE(s);
/* ACPI specs 3.0, 4.7.2.5 */
acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
if (s->dev.config[0x5b] & (1 << 1)) {
if (d->config[0x5b] & (1 << 1)) {
if (s->smi_irq) {
qemu_irq_raise(s->smi_irq);
}
@ -143,24 +151,27 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
static void pm_io_space_update(PIIX4PMState *s)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t pm_io_base;
pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
pm_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
pm_io_base &= 0xffc0;
memory_region_transaction_begin();
memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
memory_region_set_enabled(&s->io, d->config[0x80] & 1);
memory_region_set_address(&s->io, pm_io_base);
memory_region_transaction_commit();
}
static void smbus_io_space_update(PIIX4PMState *s)
{
s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90));
PCIDevice *d = PCI_DEVICE(s);
s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
s->smb_io_base &= 0xffc0;
memory_region_transaction_begin();
memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1);
memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
memory_region_set_address(&s->smb.io, s->smb_io_base);
memory_region_transaction_commit();
}
@ -239,7 +250,7 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
int ret, i;
uint16_t temp;
ret = pci_device_load(&s->dev, f);
ret = pci_device_load(PCI_DEVICE(s), f);
if (ret < 0) {
return ret;
}
@ -283,7 +294,7 @@ static const VMStateDescription vmstate_acpi = {
.load_state_old = acpi_load_old,
.post_load = vmstate_acpi_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
@ -300,7 +311,7 @@ static const VMStateDescription vmstate_acpi = {
static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
{
BusChild *kid, *next;
BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
BusState *bus = qdev_get_parent_bus(DEVICE(s));
int slot = ffs(slots) - 1;
bool slot_free = true;
@ -326,8 +337,7 @@ static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
static void piix4_update_hotplug(PIIX4PMState *s)
{
PCIDevice *dev = &s->dev;
BusState *bus = qdev_get_parent_bus(&dev->qdev);
BusState *bus = qdev_get_parent_bus(DEVICE(s));
BusChild *kid, *next;
/* Execute any pending removes during reset */
@ -355,7 +365,8 @@ static void piix4_update_hotplug(PIIX4PMState *s)
static void piix4_reset(void *opaque)
{
PIIX4PMState *s = opaque;
uint8_t *pci_conf = s->dev.config;
PCIDevice *d = PCI_DEVICE(s);
uint8_t *pci_conf = d->config;
pci_conf[0x58] = 0;
pci_conf[0x59] = 0;
@ -383,10 +394,11 @@ static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
static void piix4_pm_machine_ready(Notifier *n, void *opaque)
{
PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
MemoryRegion *io_as = pci_address_space_io(&s->dev);
PCIDevice *d = PCI_DEVICE(s);
MemoryRegion *io_as = pci_address_space_io(d);
uint8_t *pci_conf;
pci_conf = s->dev.config;
pci_conf = d->config;
pci_conf[0x5f] = 0x10 |
(memory_region_present(io_as, 0x378) ? 0x80 : 0);
pci_conf[0x63] = 0x60;
@ -396,10 +408,10 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
static int piix4_pm_initfn(PCIDevice *dev)
{
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
PIIX4PMState *s = PIIX4_PM(dev);
uint8_t *pci_conf;
pci_conf = s->dev.config;
pci_conf = dev->config;
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
pci_conf[0x09] = 0x00;
@ -419,7 +431,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
pci_conf[0x90] = s->smb_io_base | 1;
pci_conf[0x91] = s->smb_io_base >> 8;
pci_conf[0xd2] = 0x09;
pm_smbus_init(&s->dev.qdev, &s->smb);
pm_smbus_init(DEVICE(dev), &s->smb);
memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
memory_region_add_subregion(pci_address_space_io(dev),
s->smb_io_base, &s->smb.io);
@ -450,18 +462,18 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int kvm_enabled, FWCfgState *fw_cfg)
{
PCIDevice *dev;
DeviceState *dev;
PIIX4PMState *s;
dev = pci_create(bus, devfn, "PIIX4_PM");
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
s = DO_UPCAST(PIIX4PMState, dev, dev);
s = PIIX4_PM(dev);
s->irq = sci_irq;
s->smi_irq = smi_irq;
s->kvm_enabled = kvm_enabled;
qdev_init_nofail(&dev->qdev);
qdev_init_nofail(dev);
if (fw_cfg) {
uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
@ -501,7 +513,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo piix4_pm_info = {
.name = "PIIX4_PM",
.name = TYPE_PIIX4_PM,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIX4PMState),
.class_init = piix4_pm_class_init,
@ -679,7 +691,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
"acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
&s->io_pci);
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu);
memory_region_init_io(&s->io_cpu, OBJECT(s), &cpu_hotplug_ops, s,
@ -705,8 +717,7 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
PCIHotplugState state)
{
int slot = PCI_SLOT(dev->devfn);
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
PCI_DEVICE(qdev));
PIIX4PMState *s = PIIX4_PM(qdev);
/* Don't send event when device is enabled during qemu machine creation:
* it is present on boot, no hotplug event is necessary. We do send an

130
hw/block/fdc.c
View File

@ -544,8 +544,14 @@ struct FDCtrl {
uint8_t timer1;
};
#define TYPE_SYSBUS_FDC "sysbus-fdc"
#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
typedef struct FDCtrlSysBus {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
struct FDCtrl state;
} FDCtrlSysBus;
@ -773,7 +779,7 @@ static const VMStateDescription vmstate_fdc = {
static void fdctrl_external_reset_sysbus(DeviceState *d)
{
FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
FDCtrlSysBus *sys = SYSBUS_FDC(d);
FDCtrl *s = &sys->state;
fdctrl_reset(s, 0);
@ -1991,7 +1997,7 @@ static const BlockDevOps fdctrl_block_ops = {
};
/* Init functions */
static int fdctrl_connect_drives(FDCtrl *fdctrl)
static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
{
unsigned int i;
FDrive *drive;
@ -2002,12 +2008,12 @@ static int fdctrl_connect_drives(FDCtrl *fdctrl)
if (drive->bs) {
if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
error_report("fdc doesn't support drive option werror");
return -1;
error_setg(errp, "fdc doesn't support drive option werror");
return;
}
if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) {
error_report("fdc doesn't support drive option rerror");
return -1;
error_setg(errp, "fdc doesn't support drive option rerror");
return;
}
}
@ -2017,7 +2023,6 @@ static int fdctrl_connect_drives(FDCtrl *fdctrl)
bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
}
}
return 0;
}
ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
@ -2047,10 +2052,11 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
{
FDCtrl *fdctrl;
DeviceState *dev;
SysBusDevice *sbd;
FDCtrlSysBus *sys;
dev = qdev_create(NULL, "sysbus-fdc");
sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
dev = qdev_create(NULL, TYPE_SYSBUS_FDC);
sys = SYSBUS_FDC(dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
if (fds[0]) {
@ -2060,8 +2066,9 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
}
qdev_init_nofail(dev);
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
sbd = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(sbd, 0, irq);
sysbus_mmio_map(sbd, 0, mmio_base);
}
void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
@ -2075,13 +2082,13 @@ void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
}
qdev_init_nofail(dev);
sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, io_base);
sys = SYSBUS_FDC(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
*fdc_tc = qdev_get_gpio_in(dev, 0);
}
static int fdctrl_init_common(FDCtrl *fdctrl)
static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
{
int i, j;
static int command_tables_inited = 0;
@ -2102,15 +2109,16 @@ static int fdctrl_init_common(FDCtrl *fdctrl)
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
fdctrl->fifo_size = 512;
fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
fdctrl_result_timer, fdctrl);
fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */
fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
fdctrl->num_floppies = MAX_FD;
if (fdctrl->dma_chann != -1)
if (fdctrl->dma_chann != -1) {
DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
return fdctrl_connect_drives(fdctrl);
}
fdctrl_connect_drives(fdctrl, errp);
}
static const MemoryRegionPortio fdc_portio_list[] = {
@ -2124,7 +2132,7 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
ISADevice *isadev = ISA_DEVICE(dev);
FDCtrlISABus *isa = ISA_FDC(dev);
FDCtrl *fdctrl = &isa->state;
int ret;
Error *err = NULL;
isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
"fdc");
@ -2133,9 +2141,9 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
fdctrl->dma_chann = isa->dma;
qdev_set_legacy_instance_id(dev, isa->iobase, 2);
ret = fdctrl_init_common(fdctrl);
if (ret < 0) {
error_setg(errp, "Floppy init failed.");
fdctrl_realize_common(fdctrl, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
@ -2143,38 +2151,62 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
add_boot_device_path(isa->bootindexB, dev, "/floppy@1");
}
static int sysbus_fdc_init1(SysBusDevice *dev)
static void sysbus_fdc_initfn(Object *obj)
{
FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
int ret;
memory_region_init_io(&fdctrl->iomem, OBJECT(sys), &fdctrl_mem_ops, fdctrl,
memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
"fdc", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
fdctrl->dma_chann = -1;
qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
ret = fdctrl_init_common(fdctrl);
return ret;
}
static int sun4m_fdc_init1(SysBusDevice *dev)
static void sysbus_fdc_realize(DeviceState *dev, Error **errp)
{
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
FDCtrlSysBus *sys = SYSBUS_FDC(dev);
FDCtrl *fdctrl = &sys->state;
SysBusDevice *b = SYS_BUS_DEVICE(dev);
Error *err = NULL;
memory_region_init_io(&fdctrl->iomem, OBJECT(dev), &fdctrl_mem_strict_ops,
sysbus_init_mmio(b, &fdctrl->iomem);
sysbus_init_irq(b, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
fdctrl->dma_chann = -1;
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
fdctrl_realize_common(fdctrl, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
}
static void sun4m_fdc_initfn(Object *obj)
{
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
fdctrl, "fdctrl", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
}
static void sun4m_fdc_realize(DeviceState *dev, Error **errp)
{
FDCtrlSysBus *sys = SYSBUS_FDC(dev);
FDCtrl *fdctrl = &sys->state;
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
sysbus_init_mmio(sbd, &fdctrl->iomem);
sysbus_init_irq(sbd, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
fdctrl->sun4m = 1;
qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
return fdctrl_init_common(fdctrl);
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
fdctrl_realize_common(fdctrl, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
}
FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
@ -2245,18 +2277,18 @@ static Property sysbus_fdc_properties[] = {
static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sysbus_fdc_init1;
dc->realize = sysbus_fdc_realize;
dc->reset = fdctrl_external_reset_sysbus;
dc->vmsd = &vmstate_sysbus_fdc;
dc->props = sysbus_fdc_properties;
}
static const TypeInfo sysbus_fdc_info = {
.name = "sysbus-fdc",
.name = TYPE_SYSBUS_FDC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FDCtrlSysBus),
.instance_init = sysbus_fdc_initfn,
.class_init = sysbus_fdc_class_init,
};
@ -2268,9 +2300,8 @@ static Property sun4m_fdc_properties[] = {
static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sun4m_fdc_init1;
dc->realize = sun4m_fdc_realize;
dc->reset = fdctrl_external_reset_sysbus;
dc->vmsd = &vmstate_sysbus_fdc;
dc->props = sun4m_fdc_properties;
@ -2280,6 +2311,7 @@ static const TypeInfo sun4m_fdc_info = {
.name = "SUNW,fdtwo",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FDCtrlSysBus),
.instance_init = sun4m_fdc_initfn,
.class_init = sun4m_fdc_class_init,
};

33
hw/block/pflash_cfi01.c
View File

@ -60,8 +60,14 @@ do { \
#define DPRINTF(fmt, ...) do { } while (0)
#endif
#define TYPE_CFI_PFLASH01 "cfi.pflash01"
#define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
struct pflash_t {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
BlockDriverState *bs;
uint32_t nb_blocs;
uint64_t sector_len;
@ -563,9 +569,9 @@ static const MemoryRegionOps pflash_cfi01_ops_le = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pflash_cfi01_init(SysBusDevice *dev)
static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
{
pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev);
pflash_t *pfl = CFI_PFLASH01(dev);
uint64_t total_len;
int ret;
@ -584,7 +590,7 @@ static int pflash_cfi01_init(SysBusDevice *dev)
pfl->name, total_len);
vmstate_register_ram(&pfl->mem, DEVICE(pfl));
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
sysbus_init_mmio(dev, &pfl->mem);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
if (pfl->bs) {
/* read the initial flash content */
@ -593,7 +599,8 @@ static int pflash_cfi01_init(SysBusDevice *dev)
if (ret < 0) {
vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
memory_region_destroy(&pfl->mem);
return 1;
error_setg(errp, "failed to read the initial flash content");
return;
}
}
@ -690,8 +697,6 @@ static int pflash_cfi01_init(SysBusDevice *dev)
pfl->cfi_table[0x3c] = 0x00;
pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
return 0;
}
static Property pflash_cfi01_properties[] = {
@ -711,16 +716,15 @@ static Property pflash_cfi01_properties[] = {
static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pflash_cfi01_init;
dc->realize = pflash_cfi01_realize;
dc->props = pflash_cfi01_properties;
dc->vmsd = &vmstate_pflash;
}
static const TypeInfo pflash_cfi01_info = {
.name = "cfi.pflash01",
.name = TYPE_CFI_PFLASH01,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct pflash_t),
.class_init = pflash_cfi01_class_init,
@ -741,10 +745,7 @@ pflash_t *pflash_cfi01_register(hwaddr base,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be)
{
DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev),
"cfi.pflash01");
DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01);
if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
abort();
@ -760,8 +761,8 @@ pflash_t *pflash_cfi01_register(hwaddr base,
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
sysbus_mmio_map(busdev, 0, base);
return pfl;
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return CFI_PFLASH01(dev);
}
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)

36
hw/block/pflash_cfi02.c
View File

@ -55,8 +55,14 @@ do { \
#define PFLASH_LAZY_ROMD_THRESHOLD 42
#define TYPE_CFI_PFLASH02 "cfi.pflash02"
#define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
struct pflash_t {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
BlockDriverState *bs;
uint32_t sector_len;
uint32_t nb_blocs;
@ -586,9 +592,9 @@ static const MemoryRegionOps pflash_cfi02_ops_le = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pflash_cfi02_init(SysBusDevice *dev)
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
{
pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev);
pflash_t *pfl = CFI_PFLASH02(dev);
uint32_t chip_len;
int ret;
@ -610,14 +616,16 @@ static int pflash_cfi02_init(SysBusDevice *dev)
/* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
if (ret < 0) {
g_free(pfl);
return 1;
vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
memory_region_destroy(&pfl->orig_mem);
error_setg(errp, "failed to read the initial flash content");
return;
}
}
pflash_setup_mappings(pfl);
pfl->rom_mode = 1;
sysbus_init_mmio(dev, &pfl->mem);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
if (pfl->bs) {
pfl->ro = bdrv_is_read_only(pfl->bs);
@ -706,8 +714,6 @@ static int pflash_cfi02_init(SysBusDevice *dev)
pfl->cfi_table[0x3b] = 0x00;
pfl->cfi_table[0x3c] = 0x00;
return 0;
}
static Property pflash_cfi02_properties[] = {
@ -730,14 +736,13 @@ static Property pflash_cfi02_properties[] = {
static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pflash_cfi02_init;
dc->realize = pflash_cfi02_realize;
dc->props = pflash_cfi02_properties;
}
static const TypeInfo pflash_cfi02_info = {
.name = "cfi.pflash02",
.name = TYPE_CFI_PFLASH02,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct pflash_t),
.class_init = pflash_cfi02_class_init,
@ -760,10 +765,7 @@ pflash_t *pflash_cfi02_register(hwaddr base,
uint16_t unlock_addr0, uint16_t unlock_addr1,
int be)
{
DeviceState *dev = qdev_create(NULL, "cfi.pflash02");
SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev),
"cfi.pflash02");
DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH02);
if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
abort();
@ -782,6 +784,6 @@ pflash_t *pflash_cfi02_register(hwaddr base,
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
sysbus_mmio_map(busdev, 0, base);
return pfl;
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return CFI_PFLASH02(dev);
}

36
hw/display/vmware_vga.c
View File

@ -81,8 +81,16 @@ struct vmsvga_state_s {
int redraw_fifo_first, redraw_fifo_last;
};
#define TYPE_VMWARE_SVGA "vmware-svga"
#define VMWARE_SVGA(obj) \
OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
struct pci_vmsvga_state_s {
PCIDevice card;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
struct vmsvga_state_s chip;
MemoryRegion io_bar;
};
@ -787,7 +795,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
case SVGA_REG_FB_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
ret = pci_get_bar_addr(&pci_vmsvga->card, 1);
ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
break;
}
@ -823,7 +831,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
case SVGA_REG_MEM_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
ret = pci_get_bar_addr(&pci_vmsvga->card, 2);
ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
break;
}
@ -1092,8 +1100,7 @@ static void vmsvga_update_display(void *opaque)
static void vmsvga_reset(DeviceState *dev)
{
struct pci_vmsvga_state_s *pci =
DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
struct vmsvga_state_s *s = &pci->chip;
s->index = 0;
@ -1172,7 +1179,7 @@ static const VMStateDescription vmstate_vmware_vga = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
vmstate_vmware_vga_internal, struct vmsvga_state_s),
VMSTATE_END_OF_LIST()
@ -1250,24 +1257,23 @@ static const MemoryRegionOps vmsvga_io_ops = {
static int pci_vmsvga_initfn(PCIDevice *dev)
{
struct pci_vmsvga_state_s *s =
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
dev->config[PCI_LATENCY_TIMER] = 0x40;
dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
"vmsvga-io", 0x10);
memory_region_set_flush_coalesced(&s->io_bar);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
vmsvga_init(DEVICE(dev), &s->chip,
pci_address_space(dev), pci_address_space_io(dev));
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->chip.vga.vram);
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
&s->chip.fifo_ram);
if (!dev->rom_bar) {
@ -1303,7 +1309,7 @@ static void vmsvga_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo vmsvga_info = {
.name = "vmware-svga",
.name = TYPE_VMWARE_SVGA,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(struct pci_vmsvga_state_s),
.class_init = vmsvga_class_init,

2
hw/i2c/exynos4210_i2c.c
View File

@ -271,7 +271,7 @@ static const MemoryRegionOps exynos4210_i2c_ops = {
};
static const VMStateDescription exynos4210_i2c_vmstate = {
.name = TYPE_EXYNOS4_I2C,
.name = "exynos4210.i2c",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {

18
hw/i386/kvm/clock.c
View File

@ -22,8 +22,14 @@
#include <linux/kvm.h>
#include <linux/kvm_para.h>
#define TYPE_KVM_CLOCK "kvmclock"
#define KVM_CLOCK(obj) OBJECT_CHECK(KVMClockState, (obj), TYPE_KVM_CLOCK)
typedef struct KVMClockState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
uint64_t clock;
bool clock_valid;
} KVMClockState;
@ -85,12 +91,11 @@ static void kvmclock_vm_state_change(void *opaque, int running,
}
}
static int kvmclock_init(SysBusDevice *dev)
static void kvmclock_realize(DeviceState *dev, Error **errp)
{
KVMClockState *s = FROM_SYSBUS(KVMClockState, dev);
KVMClockState *s = KVM_CLOCK(dev);
qemu_add_vm_change_state_handler(kvmclock_vm_state_change, s);
return 0;
}
static const VMStateDescription kvmclock_vmsd = {
@ -107,15 +112,14 @@ static const VMStateDescription kvmclock_vmsd = {
static void kvmclock_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = kvmclock_init;
dc->realize = kvmclock_realize;
dc->no_user = 1;
dc->vmsd = &kvmclock_vmsd;
}
static const TypeInfo kvmclock_info = {
.name = "kvmclock",
.name = TYPE_KVM_CLOCK,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(KVMClockState),
.class_init = kvmclock_class_init,
@ -129,7 +133,7 @@ void kvmclock_create(void)
if (kvm_enabled() &&
cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE) |
(1ULL << KVM_FEATURE_CLOCKSOURCE2))) {
sysbus_create_simple("kvmclock", -1, NULL);
sysbus_create_simple(TYPE_KVM_CLOCK, -1, NULL);
}
}

12
hw/i386/kvmvapic.c
View File

@ -703,19 +703,18 @@ static const MemoryRegionOps vapic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int vapic_init(SysBusDevice *dev)
static void vapic_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
VAPICROMState *s = VAPIC(dev);
memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2);
sysbus_add_io(dev, VAPIC_IO_PORT, &s->io);
sysbus_init_ioports(dev, VAPIC_IO_PORT, 2);
sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io);
sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2);
option_rom[nb_option_roms].name = "kvmvapic.bin";
option_rom[nb_option_roms].bootindex = -1;
nb_option_roms++;
return 0;
}
static void do_vapic_enable(void *data)
@ -812,13 +811,12 @@ static const VMStateDescription vmstate_vapic = {
static void vapic_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->no_user = 1;
dc->reset = vapic_reset;
dc->vmsd = &vmstate_vapic;
sc->init = vapic_init;
dc->realize = vapic_realize;
}
static const TypeInfo vapic_type = {

4
hw/i386/pc_q35.c
View File

@ -60,6 +60,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
const char *boot_device = args->boot_device;
ram_addr_t below_4g_mem_size, above_4g_mem_size;
Q35PCIHost *q35_host;
PCIHostState *phb;
PCIBus *host_bus;
PCIDevice *lpc;
BusState *idebus[MAX_SATA_PORTS];
@ -139,7 +140,8 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
q35_host->mch.guest_info = guest_info;
/* pci */
qdev_init_nofail(DEVICE(q35_host));
host_bus = q35_host->host.pci.bus;
phb = PCI_HOST_BRIDGE(q35_host);
host_bus = phb->bus;
/* create ISA bus */
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,

39
hw/ide/ahci.c
View File

@ -117,12 +117,13 @@ static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
{
struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
PCIDevice *pci_dev = PCI_DEVICE(d);
DPRINTF(0, "raise irq\n");
if (msi_enabled(&d->card)) {
msi_notify(&d->card, 0);
if (msi_enabled(pci_dev)) {
msi_notify(pci_dev, 0);
} else {
qemu_irq_raise(s->irq);
}
@ -130,11 +131,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
{
struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
DPRINTF(0, "lower irq\n");
if (!msi_enabled(&d->card)) {
if (!msi_enabled(PCI_DEVICE(d))) {
qemu_irq_lower(s->irq);
}
}
@ -1285,8 +1286,14 @@ const VMStateDescription vmstate_ahci = {
},
};
#define TYPE_SYSBUS_AHCI "sysbus-ahci"
#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
typedef struct SysbusAHCIState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
AHCIState ahci;
uint32_t num_ports;
} SysbusAHCIState;
@ -1302,19 +1309,20 @@ static const VMStateDescription vmstate_sysbus_ahci = {
static void sysbus_ahci_reset(DeviceState *dev)
{
SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev);
SysbusAHCIState *s = SYSBUS_AHCI(dev);
ahci_reset(&s->ahci);
}
static int sysbus_ahci_init(SysBusDevice *dev)
static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
{
SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev);
ahci_init(&s->ahci, &dev->qdev, NULL, s->num_ports);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
SysbusAHCIState *s = SYSBUS_AHCI(dev);
sysbus_init_mmio(dev, &s->ahci.mem);
sysbus_init_irq(dev, &s->ahci.irq);
return 0;
ahci_init(&s->ahci, dev, NULL, s->num_ports);
sysbus_init_mmio(sbd, &s->ahci.mem);
sysbus_init_irq(sbd, &s->ahci.irq);
}
static Property sysbus_ahci_properties[] = {
@ -1324,17 +1332,16 @@ static Property sysbus_ahci_properties[] = {
static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sbc->init = sysbus_ahci_init;
dc->realize = sysbus_ahci_realize;
dc->vmsd = &vmstate_sysbus_ahci;
dc->props = sysbus_ahci_properties;
dc->reset = sysbus_ahci_reset;
}
static const TypeInfo sysbus_ahci_info = {
.name = "sysbus-ahci",
.name = TYPE_SYSBUS_AHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SysbusAHCIState),
.class_init = sysbus_ahci_class_init,

10
hw/ide/ahci.h
View File

@ -301,10 +301,18 @@ typedef struct AHCIState {
} AHCIState;
typedef struct AHCIPCIState {
PCIDevice card;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
AHCIState ahci;
} AHCIPCIState;
#define TYPE_ICH9_AHCI "ich9-ahci"
#define ICH_AHCI(obj) \
OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \

32
hw/ide/ich.c
View File

@ -84,7 +84,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
.unmigratable = 1, /* Still buggy under I/O load */
.version_id = 1,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(card, AHCIPCIState),
VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
VMSTATE_AHCI(ahci, AHCIPCIState),
VMSTATE_END_OF_LIST()
},
@ -92,7 +92,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
static void pci_ich9_reset(DeviceState *dev)
{
struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
AHCIPCIState *d = ICH_AHCI(dev);
ahci_reset(&d->ahci);
}
@ -102,34 +102,34 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
int sata_cap_offset;
uint8_t *sata_cap;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
d = ICH_AHCI(dev);
ahci_init(&d->ahci, &dev->qdev, pci_get_address_space(dev), 6);
ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
pci_config_set_interrupt_pin(d->card.config, 1);
dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
pci_config_set_interrupt_pin(dev->config, 1);
/* XXX Software should program this register */
d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
msi_init(dev, 0x50, 1, true, false);
d->ahci.irq = d->card.irq[0];
d->ahci.irq = dev->irq[0];
pci_register_bar(&d->card, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&d->ahci.idp);
pci_register_bar(&d->card, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
&d->ahci.mem);
sata_cap_offset = pci_add_capability(&d->card, PCI_CAP_ID_SATA,
sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
if (sata_cap_offset < 0) {
return sata_cap_offset;
}
sata_cap = d->card.config + sata_cap_offset;
sata_cap = dev->config + sata_cap_offset;
pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
pci_set_long(sata_cap + SATA_CAP_BAR,
(ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
@ -141,7 +141,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
static void pci_ich9_uninit(PCIDevice *dev)
{
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
d = ICH_AHCI(dev);
msi_uninit(dev);
ahci_uninit(&d->ahci);
@ -163,7 +163,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo ich_ahci_info = {
.name = "ich9-ahci",
.name = TYPE_ICH9_AHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(AHCIPCIState),
.class_init = ich_ahci_class_init,

12
hw/intc/ioapic_common.c
View File

@ -57,23 +57,22 @@ static int ioapic_dispatch_post_load(void *opaque, int version_id)
return 0;
}
static int ioapic_init_common(SysBusDevice *dev)
static void ioapic_common_realize(DeviceState *dev, Error **errp)
{
IOAPICCommonState *s = IOAPIC_COMMON(dev);
IOAPICCommonClass *info;
static int ioapic_no;
if (ioapic_no >= MAX_IOAPICS) {
return -1;
error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS);
return;
}
info = IOAPIC_COMMON_GET_CLASS(s);
info->init(s, ioapic_no);
sysbus_init_mmio(&s->busdev, &s->io_memory);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory);
ioapic_no++;
return 0;
}
static const VMStateDescription vmstate_ioapic_common = {
@ -95,10 +94,9 @@ static const VMStateDescription vmstate_ioapic_common = {
static void ioapic_common_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
sc->init = ioapic_init_common;
dc->realize = ioapic_common_realize;
dc->vmsd = &vmstate_ioapic_common;
dc->no_user = 1;
}

8
hw/isa/isa-bus.c
View File

@ -192,18 +192,10 @@ static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent)
}
}
static int isabus_bridge_init(SysBusDevice *dev)
{
/* nothing */
return 0;
}
static void isabus_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = isabus_bridge_init;
dc->fw_name = "isa";
dc->no_user = 1;
}

59
hw/misc/ivshmem.c
View File

@ -48,6 +48,10 @@
#define IVSHMEM_DPRINTF(fmt, ...)
#endif
#define TYPE_IVSHMEM "ivshmem"
#define IVSHMEM(obj) \
OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
typedef struct Peer {
int nb_eventfds;
EventNotifier *eventfds;
@ -59,7 +63,10 @@ typedef struct EventfdEntry {
} EventfdEntry;
typedef struct IVShmemState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
uint32_t intrmask;
uint32_t intrstatus;
uint32_t doorbell;
@ -116,6 +123,7 @@ static inline bool is_power_of_two(uint64_t x) {
/* accessing registers - based on rtl8139 */
static void ivshmem_update_irq(IVShmemState *s, int val)
{
PCIDevice *d = PCI_DEVICE(s);
int isr;
isr = (s->intrstatus & s->intrmask) & 0xffffffff;
@ -125,7 +133,7 @@ static void ivshmem_update_irq(IVShmemState *s, int val)
isr ? 1 : 0, s->intrstatus, s->intrmask);
}
qemu_set_irq(s->dev.irq[0], (isr != 0));
qemu_set_irq(d->irq[0], (isr != 0));
}
static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
@ -296,7 +304,7 @@ static CharDriverState* create_eventfd_chr_device(void * opaque, EventNotifier *
/* if MSI is supported we need multiple interrupts */
if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
s->eventfd_table[vector].pdev = &s->dev;
s->eventfd_table[vector].pdev = PCI_DEVICE(s);
s->eventfd_table[vector].vector = vector;
qemu_chr_add_handlers(chr, ivshmem_can_receive, fake_irqfd,
@ -341,11 +349,11 @@ static void create_shared_memory_BAR(IVShmemState *s, int fd) {
memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2",
s->ivshmem_size, ptr);
vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
vmstate_register_ram(&s->ivshmem, DEVICE(s));
memory_region_add_subregion(&s->bar, 0, &s->ivshmem);
/* region for shared memory */
pci_register_bar(&s->dev, 2, s->ivshmem_attr, &s->bar);
pci_register_bar(PCI_DEVICE(s), 2, s->ivshmem_attr, &s->bar);
}
static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
@ -469,7 +477,7 @@ static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)
incoming_fd, 0);
memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s),
"ivshmem.bar2", s->ivshmem_size, map_ptr);
vmstate_register_ram(&s->ivshmem, &s->dev.qdev);
vmstate_register_ram(&s->ivshmem, DEVICE(s));
IVSHMEM_DPRINTF("guest h/w addr = %" PRIu64 ", size = %" PRIu64 "\n",
s->ivshmem_offset, s->ivshmem_size);
@ -521,20 +529,21 @@ static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)
* we just enable all vectors on init and after reset. */
static void ivshmem_use_msix(IVShmemState * s)
{
PCIDevice *d = PCI_DEVICE(s);
int i;
if (!msix_present(&s->dev)) {
if (!msix_present(d)) {
return;
}
for (i = 0; i < s->vectors; i++) {
msix_vector_use(&s->dev, i);
msix_vector_use(d, i);
}
}
static void ivshmem_reset(DeviceState *d)
{
IVShmemState *s = DO_UPCAST(IVShmemState, dev.qdev, d);
IVShmemState *s = IVSHMEM(d);
s->intrstatus = 0;
ivshmem_use_msix(s);
@ -569,7 +578,7 @@ static uint64_t ivshmem_get_size(IVShmemState * s) {
static void ivshmem_setup_msi(IVShmemState * s)
{
if (msix_init_exclusive_bar(&s->dev, s->vectors, 1)) {
if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) {
IVSHMEM_DPRINTF("msix initialization failed\n");
exit(1);
}
@ -585,12 +594,13 @@ static void ivshmem_setup_msi(IVShmemState * s)
static void ivshmem_save(QEMUFile* f, void *opaque)
{
IVShmemState *proxy = opaque;
PCIDevice *pci_dev = PCI_DEVICE(proxy);
IVSHMEM_DPRINTF("ivshmem_save\n");
pci_device_save(&proxy->dev, f);
pci_device_save(pci_dev, f);
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
msix_save(&proxy->dev, f);
msix_save(pci_dev, f);
} else {
qemu_put_be32(f, proxy->intrstatus);
qemu_put_be32(f, proxy->intrmask);
@ -603,6 +613,7 @@ static int ivshmem_load(QEMUFile* f, void *opaque, int version_id)
IVSHMEM_DPRINTF("ivshmem_load\n");
IVShmemState *proxy = opaque;
PCIDevice *pci_dev = PCI_DEVICE(proxy);
int ret;
if (version_id > 0) {
@ -614,13 +625,13 @@ static int ivshmem_load(QEMUFile* f, void *opaque, int version_id)
return -EINVAL;
}
ret = pci_device_load(&proxy->dev, f);
ret = pci_device_load(pci_dev, f);
if (ret) {
return ret;
}
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
msix_load(&proxy->dev, f);
msix_load(pci_dev, f);
ivshmem_use_msix(proxy);
} else {
proxy->intrstatus = qemu_get_be32(f);
@ -639,7 +650,7 @@ static void ivshmem_write_config(PCIDevice *pci_dev, uint32_t address,
static int pci_ivshmem_init(PCIDevice *dev)
{
IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
IVShmemState *s = IVSHMEM(dev);
uint8_t *pci_conf;
if (s->sizearg == NULL)
@ -648,7 +659,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
s->ivshmem_size = ivshmem_get_size(s);
}
register_savevm(&s->dev.qdev, "ivshmem", 0, 0, ivshmem_save, ivshmem_load,
register_savevm(DEVICE(dev), "ivshmem", 0, 0, ivshmem_save, ivshmem_load,
dev);
/* IRQFD requires MSI */
@ -678,7 +689,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
migrate_add_blocker(s->migration_blocker);
}
pci_conf = s->dev.config;
pci_conf = dev->config;
pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_config_set_interrupt_pin(pci_conf, 1);
@ -689,7 +700,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
"ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
/* region for registers*/
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->ivshmem_mmio);
memory_region_init(&s->bar, OBJECT(s), "ivshmem-bar2-container", s->ivshmem_size);
@ -723,7 +734,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
/* allocate/initialize space for interrupt handling */
s->peers = g_malloc0(s->nb_peers * sizeof(Peer));
pci_register_bar(&s->dev, 2, s->ivshmem_attr, &s->bar);
pci_register_bar(dev, 2, s->ivshmem_attr, &s->bar);
s->eventfd_chr = g_malloc0(s->vectors * sizeof(CharDriverState *));
@ -764,14 +775,14 @@ static int pci_ivshmem_init(PCIDevice *dev)
}
s->dev.config_write = ivshmem_write_config;
dev->config_write = ivshmem_write_config;
return 0;
}
static void pci_ivshmem_uninit(PCIDevice *dev)
{
IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
IVShmemState *s = IVSHMEM(dev);
if (s->migration_blocker) {
migrate_del_blocker(s->migration_blocker);
@ -780,10 +791,10 @@ static void pci_ivshmem_uninit(PCIDevice *dev)
memory_region_destroy(&s->ivshmem_mmio);
memory_region_del_subregion(&s->bar, &s->ivshmem);
vmstate_unregister_ram(&s->ivshmem, &s->dev.qdev);
vmstate_unregister_ram(&s->ivshmem, DEVICE(dev));
memory_region_destroy(&s->ivshmem);
memory_region_destroy(&s->bar);
unregister_savevm(&dev->qdev, "ivshmem", s);
unregister_savevm(DEVICE(dev), "ivshmem", s);
}
static Property ivshmem_properties[] = {
@ -813,7 +824,7 @@ static void ivshmem_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo ivshmem_info = {
.name = "ivshmem",
.name = TYPE_IVSHMEM,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(IVShmemState),
.class_init = ivshmem_class_init,

24
hw/misc/pci-testdev.c
View File

@ -76,13 +76,21 @@ enum {
#define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))
typedef struct PCITestDevState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
MemoryRegion portio;
IOTest *tests;
int current;
} PCITestDevState;
#define TYPE_PCI_TEST_DEV "pci-testdev"
#define PCI_TEST_DEV(obj) \
OBJECT_CHECK(PCITestDevState, (obj), TYPE_PCI_TEST_DEV)
#define IOTEST_IS_MEM(i) (strcmp(IOTEST_TYPE(i), "portio"))
#define IOTEST_REGION(d, i) (IOTEST_IS_MEM(i) ? &(d)->mmio : &(d)->portio)
#define IOTEST_SIZE(i) (IOTEST_IS_MEM(i) ? IOTEST_MEMSIZE : IOTEST_IOSIZE)
@ -227,12 +235,12 @@ static const MemoryRegionOps pci_testdev_pio_ops = {
static int pci_testdev_init(PCIDevice *pci_dev)
{
PCITestDevState *d = DO_UPCAST(PCITestDevState, dev, pci_dev);
PCITestDevState *d = PCI_TEST_DEV(pci_dev);
uint8_t *pci_conf;
char *name;
int r, i;
pci_conf = d->dev.config;
pci_conf = pci_dev->config;
pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */
@ -240,8 +248,8 @@ static int pci_testdev_init(PCIDevice *pci_dev)
"pci-testdev-mmio", IOTEST_MEMSIZE * 2);
memory_region_init_io(&d->portio, OBJECT(d), &pci_testdev_pio_ops, d,
"pci-testdev-portio", IOTEST_IOSIZE * 2);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);
d->current = -1;
d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests);
@ -274,7 +282,7 @@ static int pci_testdev_init(PCIDevice *pci_dev)
static void
pci_testdev_uninit(PCIDevice *dev)
{
PCITestDevState *d = DO_UPCAST(PCITestDevState, dev, dev);
PCITestDevState *d = PCI_TEST_DEV(dev);
int i;
pci_testdev_reset(d);
@ -291,7 +299,7 @@ pci_testdev_uninit(PCIDevice *dev)
static void qdev_pci_testdev_reset(DeviceState *dev)
{
PCITestDevState *d = DO_UPCAST(PCITestDevState, dev.qdev, dev);
PCITestDevState *d = PCI_TEST_DEV(dev);
pci_testdev_reset(d);
}
@ -311,7 +319,7 @@ static void pci_testdev_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pci_testdev_info = {
.name = "pci-testdev",
.name = TYPE_PCI_TEST_DEV,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCITestDevState),
.class_init = pci_testdev_class_init,

53
hw/net/e1000.c
View File

@ -85,7 +85,10 @@ enum {
};
typedef struct E1000State_st {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
NICState *nic;
NICConf conf;
MemoryRegion mmio;
@ -138,6 +141,11 @@ typedef struct E1000State_st {
uint32_t compat_flags;
} E1000State;
#define TYPE_E1000 "e1000"
#define E1000(obj) \
OBJECT_CHECK(E1000State, (obj), TYPE_E1000)
#define defreg(x) x = (E1000_##x>>2)
enum {
defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
@ -240,6 +248,8 @@ static const uint32_t mac_reg_init[] = {
static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
PCIDevice *d = PCI_DEVICE(s);
if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
/* Only for 8257x */
val |= E1000_ICR_INT_ASSERTED;
@ -256,7 +266,7 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
*/
s->mac_reg[ICS] = val;
qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
qemu_set_irq(d->irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
}
static void
@ -553,6 +563,7 @@ xmit_seg(E1000State *s)
static void
process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_lower = le32_to_cpu(dp->lower.data);
uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
@ -610,7 +621,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
bytes = msh - tp->size;
bytes = MIN(sizeof(tp->data) - tp->size, bytes);
pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
pci_dma_read(d, addr, tp->data + tp->size, bytes);
sz = tp->size + bytes;
if (sz >= tp->hdr_len && tp->size < tp->hdr_len) {
memmove(tp->header, tp->data, tp->hdr_len);
@ -628,7 +639,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
DBGOUT(TXERR, "TCP segmentation error\n");
} else {
split_size = MIN(sizeof(tp->data) - tp->size, split_size);
pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
pci_dma_read(d, addr, tp->data + tp->size, split_size);
tp->size += split_size;
}
@ -647,6 +658,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
static uint32_t
txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
{
PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
@ -654,7 +666,7 @@ txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
dp->upper.data = cpu_to_le32(txd_upper);
pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp),
&dp->upper, sizeof(dp->upper));
return E1000_ICR_TXDW;
}
@ -670,6 +682,7 @@ static uint64_t tx_desc_base(E1000State *s)
static void
start_xmit(E1000State *s)
{
PCIDevice *d = PCI_DEVICE(s);
dma_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
@ -682,7 +695,7 @@ start_xmit(E1000State *s)
while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
base = tx_desc_base(s) +
sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
pci_dma_read(&s->dev, base, &desc, sizeof(desc));
pci_dma_read(d, base, &desc, sizeof(desc));
DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
@ -815,6 +828,7 @@ static ssize_t
e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
E1000State *s = qemu_get_nic_opaque(nc);
PCIDevice *d = PCI_DEVICE(s);
struct e1000_rx_desc desc;
dma_addr_t base;
unsigned int n, rdt;
@ -874,7 +888,7 @@ e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
desc_size = s->rxbuf_size;
}
base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
pci_dma_read(&s->dev, base, &desc, sizeof(desc));
pci_dma_read(d, base, &desc, sizeof(desc));
desc.special = vlan_special;
desc.status |= (vlan_status | E1000_RXD_STAT_DD);
if (desc.buffer_addr) {
@ -883,7 +897,7 @@ e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (copy_size > s->rxbuf_size) {
copy_size = s->rxbuf_size;
}
pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
pci_dma_write(d, le64_to_cpu(desc.buffer_addr),
buf + desc_offset + vlan_offset, copy_size);
}
desc_offset += desc_size;
@ -898,7 +912,7 @@ e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
} else { // as per intel docs; skip descriptors with null buf addr
DBGOUT(RX, "Null RX descriptor!!\n");
}
pci_dma_write(&s->dev, base, &desc, sizeof(desc));
pci_dma_write(d, base, &desc, sizeof(desc));
if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
s->mac_reg[RDH] = 0;
@ -1184,7 +1198,7 @@ static const VMStateDescription vmstate_e1000 = {
.pre_save = e1000_pre_save,
.post_load = e1000_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, E1000State),
VMSTATE_PCI_DEVICE(parent_obj, E1000State),
VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
VMSTATE_UNUSED(4), /* Was mmio_base. */
VMSTATE_UINT32(rxbuf_size, E1000State),
@ -1298,7 +1312,7 @@ e1000_cleanup(NetClientState *nc)
static void
pci_e1000_uninit(PCIDevice *dev)
{
E1000State *d = DO_UPCAST(E1000State, dev, dev);
E1000State *d = E1000(dev);
qemu_del_timer(d->autoneg_timer);
qemu_free_timer(d->autoneg_timer);
@ -1318,13 +1332,14 @@ static NetClientInfo net_e1000_info = {
static int pci_e1000_init(PCIDevice *pci_dev)
{
E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
DeviceState *dev = DEVICE(pci_dev);
E1000State *d = E1000(pci_dev);
uint8_t *pci_conf;
uint16_t checksum = 0;
int i;
uint8_t *macaddr;
pci_conf = d->dev.config;
pci_conf = pci_dev->config;
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
@ -1333,9 +1348,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)
e1000_mmio_setup(d);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
memmove(d->eeprom_data, e1000_eeprom_template,
sizeof e1000_eeprom_template);
@ -1349,11 +1364,11 @@ static int pci_e1000_init(PCIDevice *pci_dev)
d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
object_get_typename(OBJECT(d)), dev->id, d);
qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr);
add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
add_boot_device_path(d->conf.bootindex, dev, "/ethernet-phy@0");
d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
@ -1362,7 +1377,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
static void qdev_e1000_reset(DeviceState *dev)
{
E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
E1000State *d = E1000(dev);
e1000_reset(d);
}
@ -1392,7 +1407,7 @@ static void e1000_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo e1000_info = {
.name = "e1000",
.name = TYPE_E1000,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(E1000State),
.class_init = e1000_class_init,

21
hw/net/pcnet-pci.c
View File

@ -43,9 +43,16 @@
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH
#define TYPE_PCI_PCNET "pcnet"
#define PCI_PCNET(obj) \
OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
typedef struct {
PCIDevice pci_dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
PCNetState state;
MemoryRegion io_bar;
} PCIPCNetState;
@ -236,7 +243,7 @@ static const VMStateDescription vmstate_pci_pcnet = {
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
VMSTATE_END_OF_LIST()
}
@ -273,7 +280,7 @@ static void pci_pcnet_cleanup(NetClientState *nc)
static void pci_pcnet_uninit(PCIDevice *dev)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
PCIPCNetState *d = PCI_PCNET(dev);
memory_region_destroy(&d->state.mmio);
memory_region_destroy(&d->io_bar);
@ -293,7 +300,7 @@ static NetClientInfo net_pci_pcnet_info = {
static int pci_pcnet_init(PCIDevice *pci_dev)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
PCIPCNetState *d = PCI_PCNET(pci_dev);
PCNetState *s = &d->state;
uint8_t *pci_conf;
@ -329,12 +336,12 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
s->phys_mem_write = pci_physical_memory_write;
s->dma_opaque = pci_dev;
return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}
static void pci_reset(DeviceState *dev)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
PCIPCNetState *d = PCI_PCNET(dev);
pcnet_h_reset(&d->state);
}
@ -362,7 +369,7 @@ static void pcnet_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pcnet_info = {
.name = "pcnet",
.name = TYPE_PCI_PCNET,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIPCNetState),
.class_init = pcnet_class_init,

114
hw/net/rtl8139.c
View File

@ -92,6 +92,11 @@ static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
}
#endif
#define TYPE_RTL8139 "rtl8139"
#define RTL8139(obj) \
OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
/* Symbolic offsets to registers. */
enum RTL8139_registers {
MAC0 = 0, /* Ethernet hardware address. */
@ -428,7 +433,10 @@ typedef struct RTL8139TallyCounters
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
typedef struct RTL8139State {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
uint8_t phys[8]; /* mac address */
uint8_t mult[8]; /* multicast mask array */
@ -701,13 +709,14 @@ static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
static void rtl8139_update_irq(RTL8139State *s)
{
PCIDevice *d = PCI_DEVICE(s);
int isr;
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
s->IntrMask);
qemu_set_irq(s->dev.irq[0], (isr != 0));
qemu_set_irq(d->irq[0], (isr != 0));
}
static int rtl8139_RxWrap(RTL8139State *s)
@ -738,6 +747,8 @@ static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
{
PCIDevice *d = PCI_DEVICE(s);
if (s->RxBufAddr + size > s->RxBufferSize)
{
int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
@ -749,14 +760,14 @@ static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
if (size > wrapped)
{
pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
pci_dma_write(d, s->RxBuf + s->RxBufAddr,
buf, size-wrapped);
}
/* reset buffer pointer */
s->RxBufAddr = 0;
pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
pci_dma_write(d, s->RxBuf + s->RxBufAddr,
buf + (size-wrapped), wrapped);
s->RxBufAddr = wrapped;
@ -766,7 +777,7 @@ static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
}
/* non-wrapping path or overwrapping enabled */
pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
s->RxBufAddr += size;
}
@ -809,6 +820,7 @@ static int rtl8139_can_receive(NetClientState *nc)
static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
{
RTL8139State *s = qemu_get_nic_opaque(nc);
PCIDevice *d = PCI_DEVICE(s);
/* size is the length of the buffer passed to the driver */
int size = size_;
const uint8_t *dot1q_buf = NULL;
@ -973,13 +985,13 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
rxdw0 = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
rxdw1 = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
rxbufLO = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
rxbufHI = le32_to_cpu(val);
DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
@ -1047,12 +1059,12 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t
/* receive/copy to target memory */
if (dot1q_buf) {
pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
size - 2 * ETHER_ADDR_LEN);
} else {
pci_dma_write(&s->dev, rx_addr, buf, size);
pci_dma_write(d, rx_addr, buf, size);
}
if (s->CpCmd & CPlusRxChkSum)
@ -1062,7 +1074,7 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t
/* write checksum */
val = cpu_to_le32(crc32(0, buf, size_));
pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
/* first segment of received packet flag */
#define CP_RX_STATUS_FS (1<<29)
@ -1108,9 +1120,9 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t
/* update ring data */
val = cpu_to_le32(rxdw0);
pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
val = cpu_to_le32(rxdw1);
pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
/* update tally counter */
++s->tally_counters.RxOk;
@ -1197,7 +1209,7 @@ static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
static void rtl8139_reset(DeviceState *d)
{
RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
RTL8139State *s = RTL8139(d);
int i;
/* restore MAC address */
@ -1293,49 +1305,50 @@ static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
{
PCIDevice *d = PCI_DEVICE(s);
RTL8139TallyCounters *tally_counters = &s->tally_counters;
uint16_t val16;
uint32_t val32;
uint64_t val64;
val64 = cpu_to_le64(tally_counters->TxOk);
pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->RxOk);
pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->TxERR);
pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
val32 = cpu_to_le32(tally_counters->RxERR);
pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
val16 = cpu_to_le16(tally_counters->MissPkt);
pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
val16 = cpu_to_le16(tally_counters->FAE);
pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
val32 = cpu_to_le32(tally_counters->Tx1Col);
pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
val32 = cpu_to_le32(tally_counters->TxMCol);
pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
val64 = cpu_to_le64(tally_counters->RxOkPhy);
pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
val64 = cpu_to_le64(tally_counters->RxOkBrd);
pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
val32 = cpu_to_le32(tally_counters->RxOkMul);
pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
val16 = cpu_to_le16(tally_counters->TxAbt);
pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
val16 = cpu_to_le16(tally_counters->TxUndrn);
pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
}
/* Loads values of tally counters from VM state file */
@ -1364,6 +1377,8 @@ static const VMStateDescription vmstate_tally_counters = {
static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
{
DeviceState *d = DEVICE(s);
val &= 0xff;
DPRINTF("ChipCmd write val=0x%08x\n", val);
@ -1371,7 +1386,7 @@ static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
if (val & CmdReset)
{
DPRINTF("ChipCmd reset\n");
rtl8139_reset(&s->dev.qdev);
rtl8139_reset(d);
}
if (val & CmdRxEnb)
{
@ -1525,6 +1540,8 @@ static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
{
DeviceState *d = DEVICE(s);
val &= 0xff;
DPRINTF("Cfg9346 write val=0x%02x\n", val);
@ -1544,7 +1561,7 @@ static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
} else if (opmode == 0x40) {
/* Reset. */
val = 0;
rtl8139_reset(&s->dev.qdev);
rtl8139_reset(d);
}
s->Cfg9346 = val;
@ -1821,13 +1838,14 @@ static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
PCIDevice *d = PCI_DEVICE(s);
int txsize = s->TxStatus[descriptor] & 0x1fff;
uint8_t txbuffer[0x2000];
DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
txsize, s->TxAddr[descriptor]);
pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
/* Mark descriptor as transferred */
s->TxStatus[descriptor] |= TxHostOwns;
@ -1946,6 +1964,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
return 0 ;
}
PCIDevice *d = PCI_DEVICE(s);
int descriptor = s->currCPlusTxDesc;
dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
@ -1959,13 +1978,13 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
txdw0 = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
txdw1 = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
txbufLO = le32_to_cpu(val);
pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
txbufHI = le32_to_cpu(val);
DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
@ -2072,7 +2091,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
s->cplus_txbuffer_offset);
pci_dma_read(&s->dev, tx_addr,
pci_dma_read(d, tx_addr,
s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
s->cplus_txbuffer_offset += txsize;
@ -2100,7 +2119,7 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
/* update ring data */
val = cpu_to_le32(txdw0);
pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
/* Now decide if descriptor being processed is holding the last segment of packet */
if (txdw0 & CP_TX_LS)
@ -3273,7 +3292,7 @@ static const VMStateDescription vmstate_rtl8139 = {
.post_load = rtl8139_post_load,
.pre_save = rtl8139_pre_save,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, RTL8139State),
VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
VMSTATE_BUFFER(mult, RTL8139State),
VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
@ -3439,7 +3458,7 @@ static void rtl8139_cleanup(NetClientState *nc)
static void pci_rtl8139_uninit(PCIDevice *dev)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
RTL8139State *s = RTL8139(dev);
memory_region_destroy(&s->bar_io);
memory_region_destroy(&s->bar_mem);
@ -3477,10 +3496,11 @@ static NetClientInfo net_rtl8139_info = {
static int pci_rtl8139_init(PCIDevice *dev)
{
RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
RTL8139State *s = RTL8139(dev);
DeviceState *d = DEVICE(dev);
uint8_t *pci_conf;
pci_conf = s->dev.config;
pci_conf = dev->config;
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
/* TODO: start of capability list, but no capability
* list bit in status register, and offset 0xdc seems unused. */
@ -3490,8 +3510,8 @@ static int pci_rtl8139_init(PCIDevice *dev)
"rtl8139", 0x100);
memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s,
"rtl8139", 0x100);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
@ -3507,7 +3527,7 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), d->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
s->cplus_txbuffer = NULL;
@ -3518,7 +3538,7 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
add_boot_device_path(s->conf.bootindex, d, "/ethernet-phy@0");
return 0;
}
@ -3546,7 +3566,7 @@ static void rtl8139_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo rtl8139_info = {
.name = "rtl8139",
.name = TYPE_RTL8139,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(RTL8139State),
.class_init = rtl8139_class_init,

42
hw/nvram/fw_cfg.c
View File

@ -35,6 +35,7 @@
#define TYPE_FW_CFG "fw_cfg"
#define FW_CFG_NAME "fw_cfg"
#define FW_CFG_PATH "/machine/" FW_CFG_NAME
#define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
typedef struct FWCfgEntry {
uint32_t len;
@ -44,7 +45,10 @@ typedef struct FWCfgEntry {
} FWCfgEntry;
struct FWCfgState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion ctl_iomem, data_iomem, comb_iomem;
uint32_t ctl_iobase, data_iobase;
FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
@ -326,7 +330,7 @@ static const MemoryRegionOps fw_cfg_comb_mem_ops = {
static void fw_cfg_reset(DeviceState *d)
{
FWCfgState *s = DO_UPCAST(FWCfgState, busdev.qdev, d);
FWCfgState *s = FW_CFG(d);
fw_cfg_select(s, 0);
}
@ -489,12 +493,12 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
SysBusDevice *d;
FWCfgState *s;
dev = qdev_create(NULL, "fw_cfg");
dev = qdev_create(NULL, TYPE_FW_CFG);
qdev_prop_set_uint32(dev, "ctl_iobase", ctl_port);
qdev_prop_set_uint32(dev, "data_iobase", data_port);
d = SYS_BUS_DEVICE(dev);
s = DO_UPCAST(FWCfgState, busdev.qdev, dev);
s = FW_CFG(dev);
assert(!object_resolve_path(FW_CFG_PATH, NULL));
@ -522,31 +526,38 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
return s;
}
static int fw_cfg_init1(SysBusDevice *dev)
static void fw_cfg_initfn(Object *obj)
{
FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
FWCfgState *s = FW_CFG(obj);
memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, s,
"fwcfg.ctl", FW_CFG_SIZE);
sysbus_init_mmio(dev, &s->ctl_iomem);
sysbus_init_mmio(sbd, &s->ctl_iomem);
memory_region_init_io(&s->data_iomem, OBJECT(s), &fw_cfg_data_mem_ops, s,
"fwcfg.data", FW_CFG_DATA_SIZE);
sysbus_init_mmio(dev, &s->data_iomem);
sysbus_init_mmio(sbd, &s->data_iomem);
/* In case ctl and data overlap: */
memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, s,
"fwcfg", FW_CFG_SIZE);
}
static void fw_cfg_realize(DeviceState *dev, Error **errp)
{
FWCfgState *s = FW_CFG(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
if (s->ctl_iobase + 1 == s->data_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
sysbus_add_io(sbd, s->ctl_iobase, &s->comb_iomem);
} else {
if (s->ctl_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->ctl_iomem);
sysbus_add_io(sbd, s->ctl_iobase, &s->ctl_iomem);
}
if (s->data_iobase) {
sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
sysbus_add_io(sbd, s->data_iobase, &s->data_iomem);
}
}
return 0;
}
static Property fw_cfg_properties[] = {
@ -557,16 +568,14 @@ static Property fw_cfg_properties[] = {
FWCfgState *fw_cfg_find(void)
{
return OBJECT_CHECK(FWCfgState, object_resolve_path(FW_CFG_PATH, NULL),
TYPE_FW_CFG);
return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
}
static void fw_cfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = fw_cfg_init1;
dc->realize = fw_cfg_realize;
dc->no_user = 1;
dc->reset = fw_cfg_reset;
dc->vmsd = &vmstate_fw_cfg;
@ -577,6 +586,7 @@ static const TypeInfo fw_cfg_info = {
.name = TYPE_FW_CFG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FWCfgState),
.instance_init = fw_cfg_initfn,
.class_init = fw_cfg_class_init,
};

56
hw/pci-host/piix.c
View File

@ -87,7 +87,10 @@ typedef struct PIIX3State {
OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
struct PCII440FXState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion *system_memory;
MemoryRegion *pci_address_space;
MemoryRegion *ram_memory;
@ -121,22 +124,24 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i;
PCIDevice *pd = PCI_DEVICE(d);
memory_region_transaction_begin();
for (i = 0; i < 13; i++) {
pam_update(&d->pam_regions[i], i,
d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
pd->config[I440FX_PAM + ((i + 1) / 2)]);
}
smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
memory_region_transaction_commit();
}
static void i440fx_set_smm(int val, void *arg)
{
PCII440FXState *d = arg;
PCIDevice *pd = PCI_DEVICE(d);
memory_region_transaction_begin();
smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
&d->smram_region);
memory_region_transaction_commit();
}
@ -158,9 +163,10 @@ static void i440fx_write_config(PCIDevice *dev,
static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
PCII440FXState *d = opaque;
PCIDevice *pd = PCI_DEVICE(d);
int ret, i;
ret = pci_device_load(&d->dev, f);
ret = pci_device_load(pd, f);
if (ret < 0)
return ret;
i440fx_update_memory_mappings(d);
@ -191,34 +197,39 @@ static const VMStateDescription vmstate_i440fx = {
.load_state_old = i440fx_load_old,
.post_load = i440fx_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, PCII440FXState),
VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
VMSTATE_UINT8(smm_enabled, PCII440FXState),
VMSTATE_END_OF_LIST()
}
};
static int i440fx_pcihost_initfn(SysBusDevice *dev)
static void i440fx_pcihost_initfn(Object *obj)
{
PCIHostState *s = PCI_HOST_BRIDGE(obj);
memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
"pci-conf-idx", 4);
memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
"pci-conf-data", 4);
}
static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
{
PCIHostState *s = PCI_HOST_BRIDGE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&s->conf_mem, OBJECT(dev), &pci_host_conf_le_ops, s,
"pci-conf-idx", 4);
sysbus_add_io(dev, 0xcf8, &s->conf_mem);
sysbus_init_ioports(&s->busdev, 0xcf8, 4);
sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
sysbus_init_ioports(sbd, 0xcf8, 4);
memory_region_init_io(&s->data_mem, OBJECT(dev), &pci_host_data_le_ops, s,
"pci-conf-data", 4);
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
return 0;
sysbus_add_io(sbd, 0xcfc, &s->data_mem);
sysbus_init_ioports(sbd, 0xcfc, 4);
}
static int i440fx_initfn(PCIDevice *dev)
{
PCII440FXState *d = I440FX_PCI_DEVICE(dev);
d->dev.config[I440FX_SMRAM] = 0x02;
dev->config[I440FX_SMRAM] = 0x02;
cpu_smm_register(&i440fx_set_smm, d);
return 0;
@ -305,9 +316,10 @@ static PCIBus *i440fx_common_init(const char *device_name,
*piix3_devfn = piix3->dev.devfn;
ram_size = ram_size / 8 / 1024 / 1024;
if (ram_size > 255)
if (ram_size > 255) {
ram_size = 255;
(*pi440fx_state)->dev.config[0x57]=ram_size;
}
d->config[0x57] = ram_size;
i440fx_update_memory_mappings(f);
@ -640,11 +652,10 @@ static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
hc->root_bus_path = i440fx_pcihost_root_bus_path;
k->init = i440fx_pcihost_initfn;
dc->realize = i440fx_pcihost_realize;
dc->fw_name = "pci";
dc->no_user = 1;
}
@ -653,6 +664,7 @@ static const TypeInfo i440fx_pcihost_info = {
.name = "i440FX-pcihost",
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(I440FXState),
.instance_init = i440fx_pcihost_initfn,
.class_init = i440fx_pcihost_class_init,
};

68
hw/pci-host/q35.c
View File

@ -34,33 +34,27 @@
* Q35 host
*/
static int q35_host_init(SysBusDevice *dev)
static void q35_host_realize(DeviceState *dev, Error **errp)
{
PCIBus *b;
PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
Q35PCIHost *s = Q35_HOST_DEVICE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci,
"pci-conf-idx", 4);
sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci,
"pci-conf-data", 4);
sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
if (pcie_host_init(&s->host) < 0) {
return -1;
if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
error_setg(errp, "failed to initialize pcie host");
return;
}
b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
s->mch.pci_address_space, s->mch.address_space_io,
0, TYPE_PCIE_BUS);
s->host.pci.bus = b;
qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
s->mch.pci_address_space, s->mch.address_space_io,
0, TYPE_PCIE_BUS);
qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
qdev_init_nofail(DEVICE(&s->mch));
return 0;
}
static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
@ -71,7 +65,7 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
}
static Property mch_props[] = {
DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
};
@ -79,11 +73,10 @@ static Property mch_props[] = {
static void q35_host_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
hc->root_bus_path = q35_host_root_bus_path;
k->init = q35_host_init;
dc->realize = q35_host_realize;
dc->props = mch_props;
dc->fw_name = "pci";
}
@ -91,6 +84,12 @@ static void q35_host_class_init(ObjectClass *klass, void *data)
static void q35_host_initfn(Object *obj)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
PCIHostState *phb = PCI_HOST_BRIDGE(obj);
memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
"pci-conf-idx", 4);
memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
"pci-conf-data", 4);
object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
@ -113,10 +112,9 @@ static const TypeInfo q35_host_info = {
/* PCIe MMCFG */
static void mch_update_pciexbar(MCHPCIState *mch)
{
PCIDevice *pci_dev = &mch->d;
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
DeviceState *qdev = bus->parent;
Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
PCIDevice *pci_dev = PCI_DEVICE(mch);
BusState *bus = qdev_get_parent_bus(DEVICE(mch));
PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
uint64_t pciexbar;
int enable;
@ -148,18 +146,19 @@ static void mch_update_pciexbar(MCHPCIState *mch)
break;
}
addr = pciexbar & addr_mask;
pcie_host_mmcfg_update(&s->host, enable, addr, length);
pcie_host_mmcfg_update(pehb, enable, addr, length);
}
/* PAM */
static void mch_update_pam(MCHPCIState *mch)
{
PCIDevice *pd = PCI_DEVICE(mch);
int i;
memory_region_transaction_begin();
for (i = 0; i < 13; i++) {
pam_update(&mch->pam_regions[i], i,
mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
}
memory_region_transaction_commit();
}
@ -167,8 +166,10 @@ static void mch_update_pam(MCHPCIState *mch)
/* SMRAM */
static void mch_update_smram(MCHPCIState *mch)
{
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
mch->smm_enabled);
memory_region_transaction_commit();
}
@ -176,9 +177,10 @@ static void mch_update_smram(MCHPCIState *mch)
static void mch_set_smm(int smm, void *arg)
{
MCHPCIState *mch = arg;
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
&mch->smram_region);
memory_region_transaction_commit();
}
@ -228,7 +230,7 @@ static const VMStateDescription vmstate_mch = {
.minimum_version_id_old = 1,
.post_load = mch_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(d, MCHPCIState),
VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
VMSTATE_UINT8(smm_enabled, MCHPCIState),
VMSTATE_END_OF_LIST()
}

2
hw/pci/pci-hotplug-old.c
View File

@ -127,7 +127,7 @@ static int scsi_hot_add(Monitor *mon, DeviceState *adapter,
dinfo->unit = qemu_opt_get_number(dinfo->opts, "unit", -1);
dinfo->bus = scsibus->busnr;
scsidev = scsi_bus_legacy_add_drive(scsibus, dinfo->bdrv, dinfo->unit,
false, -1, NULL);
false, -1, NULL, NULL);
if (!scsidev) {
return -1;
}

36
hw/scsi/esp-pci.c
View File

@ -31,6 +31,9 @@
#define TYPE_AM53C974_DEVICE "am53c974"
#define PCI_ESP(obj) \
OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
#define DMA_CMD 0x0
#define DMA_STC 0x1
#define DMA_SPA 0x2
@ -57,7 +60,10 @@
#define SBAC_STATUS 0x1000
typedef struct PCIESPState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion io;
uint32_t dma_regs[8];
uint32_t sbac;
@ -257,7 +263,7 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
len = pci->dma_regs[DMA_WBC];
}
pci_dma_rw(&pci->dev, addr, buf, len, dir);
pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
/* update status registers */
pci->dma_regs[DMA_WBC] -= len;
@ -288,7 +294,7 @@ static const MemoryRegionOps esp_pci_io_ops = {
static void esp_pci_hard_reset(DeviceState *dev)
{
PCIESPState *pci = DO_UPCAST(PCIESPState, dev.qdev, dev);
PCIESPState *pci = PCI_ESP(dev);
esp_hard_reset(&pci->esp);
pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
| DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
@ -306,7 +312,7 @@ static const VMStateDescription vmstate_esp_pci_scsi = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PCIESPState),
VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
VMSTATE_END_OF_LIST()
@ -336,11 +342,13 @@ static const struct SCSIBusInfo esp_pci_scsi_info = {
static int esp_pci_scsi_init(PCIDevice *dev)
{
PCIESPState *pci = DO_UPCAST(PCIESPState, dev, dev);
PCIESPState *pci = PCI_ESP(dev);
DeviceState *d = DEVICE(dev);
ESPState *s = &pci->esp;
uint8_t *pci_conf;
Error *err = NULL;
pci_conf = pci->dev.config;
pci_conf = dev->config;
/* Interrupt pin A */
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
@ -352,19 +360,23 @@ static int esp_pci_scsi_init(PCIDevice *dev)
memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
"esp-io", 0x80);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
s->irq = pci->dev.irq[0];
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
s->irq = dev->irq[0];
scsi_bus_new(&s->bus, &dev->qdev, &esp_pci_scsi_info, NULL);
if (!dev->qdev.hotplugged) {
return scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_new(&s->bus, d, &esp_pci_scsi_info, NULL);
if (!d->hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_free(err);
return -1;
}
}
return 0;
}
static void esp_pci_scsi_uninit(PCIDevice *d)
{
PCIESPState *pci = DO_UPCAST(PCIESPState, dev, d);
PCIESPState *pci = PCI_ESP(d);
memory_region_destroy(&pci->io);
}

42
hw/scsi/esp.c
View File

@ -578,8 +578,14 @@ const VMStateDescription vmstate_esp = {
}
};
#define TYPE_ESP "esp"
#define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t it_shift;
ESPState esp;
@ -623,8 +629,8 @@ void esp_init(hwaddr espaddr, int it_shift,
SysBusESPState *sysbus;
ESPState *esp;
dev = qdev_create(NULL, "esp");
sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev);
dev = qdev_create(NULL, TYPE_ESP);
sysbus = ESP(dev);
esp = &sysbus->esp;
esp->dma_memory_read = dma_memory_read;
esp->dma_memory_write = dma_memory_write;
@ -652,8 +658,7 @@ static const struct SCSIBusInfo esp_scsi_info = {
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
{
DeviceState *d = opaque;
SysBusESPState *sysbus = container_of(d, SysBusESPState, busdev.qdev);
SysBusESPState *sysbus = ESP(opaque);
ESPState *s = &sysbus->esp;
switch (irq) {
@ -666,28 +671,34 @@ static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
}
}
static int sysbus_esp_init(SysBusDevice *dev)
static void sysbus_esp_realize(DeviceState *dev, Error **errp)
{
SysBusESPState *sysbus = FROM_SYSBUS(SysBusESPState, dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
SysBusESPState *sysbus = ESP(dev);
ESPState *s = &sysbus->esp;
Error *err = NULL;
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
assert(sysbus->it_shift != -1);
s->chip_id = TCHI_FAS100A;
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
sysbus, "esp", ESP_REGS << sysbus->it_shift);
sysbus_init_mmio(dev, &sysbus->iomem);
sysbus_init_mmio(sbd, &sysbus->iomem);
qdev_init_gpio_in(&dev->qdev, sysbus_esp_gpio_demux, 2);
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info, NULL);
return scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_new(&s->bus, dev, &esp_scsi_info, NULL);
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
}
static void sysbus_esp_hard_reset(DeviceState *dev)
{
SysBusESPState *sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev);
SysBusESPState *sysbus = ESP(dev);
esp_hard_reset(&sysbus->esp);
}
@ -705,15 +716,14 @@ static const VMStateDescription vmstate_sysbus_esp_scsi = {
static void sysbus_esp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sysbus_esp_init;
dc->realize = sysbus_esp_realize;
dc->reset = sysbus_esp_hard_reset;
dc->vmsd = &vmstate_sysbus_esp_scsi;
}
static const TypeInfo sysbus_esp_info = {
.name = "esp",
.name = TYPE_ESP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SysBusESPState),
.class_init = sysbus_esp_class_init,

79
hw/scsi/lsi53c895a.c
View File

@ -184,7 +184,10 @@ typedef struct lsi_request {
} lsi_request;
typedef struct {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion mmio_io;
MemoryRegion ram_io;
MemoryRegion io_io;
@ -275,6 +278,11 @@ typedef struct {
uint32_t script_ram[2048];
} LSIState;
#define TYPE_LSI53C895A "lsi53c895a"
#define LSI53C895A(obj) \
OBJECT_CHECK(LSIState, (obj), TYPE_LSI53C895A)
static inline int lsi_irq_on_rsl(LSIState *s)
{
return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE);
@ -382,7 +390,7 @@ static inline uint32_t read_dword(LSIState *s, uint32_t addr)
{
uint32_t buf;
pci_dma_read(&s->dev, addr, &buf, 4);
pci_dma_read(PCI_DEVICE(s), addr, &buf, 4);
return cpu_to_le32(buf);
}
@ -393,6 +401,7 @@ static void lsi_stop_script(LSIState *s)
static void lsi_update_irq(LSIState *s)
{
PCIDevice *d = PCI_DEVICE(s);
int level;
static int last_level;
lsi_request *p;
@ -424,7 +433,7 @@ static void lsi_update_irq(LSIState *s)
level, s->dstat, s->sist1, s->sist0);
last_level = level;
}
qemu_set_irq(s->dev.irq[0], level);
qemu_set_irq(d->irq[0], level);
if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) {
DPRINTF("Handled IRQs & disconnected, looking for pending "
@ -520,6 +529,7 @@ static void lsi_bad_selection(LSIState *s, uint32_t id)
/* Initiate a SCSI layer data transfer. */
static void lsi_do_dma(LSIState *s, int out)
{
PCIDevice *pci_dev;
uint32_t count;
dma_addr_t addr;
SCSIDevice *dev;
@ -531,6 +541,7 @@ static void lsi_do_dma(LSIState *s, int out)
return;
}
pci_dev = PCI_DEVICE(s);
dev = s->current->req->dev;
assert(dev);
@ -556,9 +567,9 @@ static void lsi_do_dma(LSIState *s, int out)
}
/* ??? Set SFBR to first data byte. */
if (out) {
pci_dma_read(&s->dev, addr, s->current->dma_buf, count);
pci_dma_read(pci_dev, addr, s->current->dma_buf, count);
} else {
pci_dma_write(&s->dev, addr, s->current->dma_buf, count);
pci_dma_write(pci_dev, addr, s->current->dma_buf, count);
}
s->current->dma_len -= count;
if (s->current->dma_len == 0) {
@ -653,7 +664,7 @@ static void lsi_request_free(LSIState *s, lsi_request *p)
static void lsi_request_cancelled(SCSIRequest *req)
{
LSIState *s = DO_UPCAST(LSIState, dev.qdev, req->bus->qbus.parent);
LSIState *s = LSI53C895A(req->bus->qbus.parent);
lsi_request *p = req->hba_private;
req->hba_private = NULL;
@ -692,7 +703,7 @@ static int lsi_queue_req(LSIState *s, SCSIRequest *req, uint32_t len)
/* Callback to indicate that the SCSI layer has completed a command. */
static void lsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
{
LSIState *s = DO_UPCAST(LSIState, dev.qdev, req->bus->qbus.parent);
LSIState *s = LSI53C895A(req->bus->qbus.parent);
int out;
out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
@ -717,7 +728,7 @@ static void lsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid
/* Callback to indicate that the SCSI layer has completed a transfer. */
static void lsi_transfer_data(SCSIRequest *req, uint32_t len)
{
LSIState *s = DO_UPCAST(LSIState, dev.qdev, req->bus->qbus.parent);
LSIState *s = LSI53C895A(req->bus->qbus.parent);
int out;
assert(req->hba_private);
@ -753,7 +764,7 @@ static void lsi_do_command(LSIState *s)
DPRINTF("Send command len=%d\n", s->dbc);
if (s->dbc > 16)
s->dbc = 16;
pci_dma_read(&s->dev, s->dnad, buf, s->dbc);
pci_dma_read(PCI_DEVICE(s), s->dnad, buf, s->dbc);
s->sfbr = buf[0];
s->command_complete = 0;
@ -804,7 +815,7 @@ static void lsi_do_status(LSIState *s)
s->dbc = 1;
status = s->status;
s->sfbr = status;
pci_dma_write(&s->dev, s->dnad, &status, 1);
pci_dma_write(PCI_DEVICE(s), s->dnad, &status, 1);
lsi_set_phase(s, PHASE_MI);
s->msg_action = 1;
lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
@ -818,7 +829,7 @@ static void lsi_do_msgin(LSIState *s)
len = s->msg_len;
if (len > s->dbc)
len = s->dbc;
pci_dma_write(&s->dev, s->dnad, s->msg, len);
pci_dma_write(PCI_DEVICE(s), s->dnad, s->msg, len);
/* Linux drivers rely on the last byte being in the SIDL. */
s->sidl = s->msg[len - 1];
s->msg_len -= len;
@ -850,7 +861,7 @@ static void lsi_do_msgin(LSIState *s)
static uint8_t lsi_get_msgbyte(LSIState *s)
{
uint8_t data;
pci_dma_read(&s->dev, s->dnad, &data, 1);
pci_dma_read(PCI_DEVICE(s), s->dnad, &data, 1);
s->dnad++;
s->dbc--;
return data;
@ -996,14 +1007,15 @@ static inline int32_t sxt24(int32_t n)
#define LSI_BUF_SIZE 4096
static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
{
PCIDevice *d = PCI_DEVICE(s);
int n;
uint8_t buf[LSI_BUF_SIZE];
DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
while (count) {
n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
pci_dma_read(&s->dev, src, buf, n);
pci_dma_write(&s->dev, dest, buf, n);
pci_dma_read(d, src, buf, n);
pci_dma_write(d, dest, buf, n);
src += n;
dest += n;
count -= n;
@ -1029,6 +1041,7 @@ static void lsi_wait_reselect(LSIState *s)
static void lsi_execute_script(LSIState *s)
{
PCIDevice *pci_dev = PCI_DEVICE(s);
uint32_t insn;
uint32_t addr, addr_high;
int opcode;
@ -1071,7 +1084,7 @@ again:
/* 32-bit Table indirect */
offset = sxt24(addr);
pci_dma_read(&s->dev, s->dsa + offset, buf, 8);
pci_dma_read(pci_dev, s->dsa + offset, buf, 8);
/* byte count is stored in bits 0:23 only */
s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
s->rbc = s->dbc;
@ -1430,7 +1443,7 @@ again:
n = (insn & 7);
reg = (insn >> 16) & 0xff;
if (insn & (1 << 24)) {
pci_dma_read(&s->dev, addr, data, n);
pci_dma_read(pci_dev, addr, data, n);
DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
addr, *(int *)data);
for (i = 0; i < n; i++) {
@ -1441,7 +1454,7 @@ again:
for (i = 0; i < n; i++) {
data[i] = lsi_reg_readb(s, reg + i);
}
pci_dma_write(&s->dev, addr, data, n);
pci_dma_write(pci_dev, addr, data, n);
}
}
}
@ -1726,7 +1739,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
lsi_execute_script(s);
}
if (val & LSI_ISTAT0_SRST) {
qdev_reset_all(&s->dev.qdev);
qdev_reset_all(DEVICE(s));
}
break;
case 0x16: /* MBOX0 */
@ -1960,7 +1973,7 @@ static const MemoryRegionOps lsi_io_ops = {
static void lsi_scsi_reset(DeviceState *dev)
{
LSIState *s = DO_UPCAST(LSIState, dev.qdev, dev);
LSIState *s = LSI53C895A(dev);
lsi_soft_reset(s);
}
@ -1983,7 +1996,7 @@ static const VMStateDescription vmstate_lsi_scsi = {
.minimum_version_id_old = 0,
.pre_save = lsi_pre_save,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, LSIState),
VMSTATE_PCI_DEVICE(parent_obj, LSIState),
VMSTATE_INT32(carry, LSIState),
VMSTATE_INT32(status, LSIState),
@ -2061,7 +2074,7 @@ static const VMStateDescription vmstate_lsi_scsi = {
static void lsi_scsi_uninit(PCIDevice *d)
{
LSIState *s = DO_UPCAST(LSIState, dev, d);
LSIState *s = LSI53C895A(d);
memory_region_destroy(&s->mmio_io);
memory_region_destroy(&s->ram_io);
@ -2080,10 +2093,12 @@ static const struct SCSIBusInfo lsi_scsi_info = {
static int lsi_scsi_init(PCIDevice *dev)
{
LSIState *s = DO_UPCAST(LSIState, dev, dev);
LSIState *s = LSI53C895A(dev);
DeviceState *d = DEVICE(dev);
uint8_t *pci_conf;
Error *err = NULL;
pci_conf = s->dev.config;
pci_conf = dev->config;
/* PCI latency timer = 255 */
pci_conf[PCI_LATENCY_TIMER] = 0xff;
@ -2097,14 +2112,18 @@ static int lsi_scsi_init(PCIDevice *dev)
memory_region_init_io(&s->io_io, OBJECT(s), &lsi_io_ops, s,
"lsi-io", 256);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
pci_register_bar(&s->dev, 1, 0, &s->mmio_io);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
pci_register_bar(dev, 1, 0, &s->mmio_io);
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
QTAILQ_INIT(&s->queue);
scsi_bus_new(&s->bus, &dev->qdev, &lsi_scsi_info, NULL);
if (!dev->qdev.hotplugged) {
return scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_new(&s->bus, d, &lsi_scsi_info, NULL);
if (!d->hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_free(err);
return -1;
}
}
return 0;
}
@ -2125,7 +2144,7 @@ static void lsi_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lsi_info = {
.name = "lsi53c895a",
.name = TYPE_LSI53C895A,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(LSIState),
.class_init = lsi_class_init,

71
hw/scsi/megasas.c
View File

@ -70,7 +70,10 @@ typedef struct MegasasCmd {
} MegasasCmd;
typedef struct MegasasState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion mmio_io;
MemoryRegion port_io;
MemoryRegion queue_io;
@ -108,6 +111,11 @@ typedef struct MegasasState {
SCSIBus bus;
} MegasasState;
#define TYPE_MEGASAS "megasas"
#define MEGASAS(obj) \
OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS)
#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
static bool megasas_intr_enabled(MegasasState *s)
@ -232,7 +240,7 @@ static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
MEGASAS_MAX_SGE);
return iov_count;
}
pci_dma_sglist_init(&cmd->qsg, &s->dev, iov_count);
pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
for (i = 0; i < iov_count; i++) {
dma_addr_t iov_pa, iov_size_p;
@ -493,6 +501,7 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
static void megasas_complete_frame(MegasasState *s, uint64_t context)
{
PCIDevice *pci_dev = PCI_DEVICE(s);
int tail, queue_offset;
/* Decrement busy count */
@ -521,12 +530,12 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
/* Notify HBA */
s->doorbell++;
if (s->doorbell == 1) {
if (msix_enabled(&s->dev)) {
if (msix_enabled(pci_dev)) {
trace_megasas_msix_raise(0);
msix_notify(&s->dev, 0);
msix_notify(pci_dev, 0);
} else {
trace_megasas_irq_raise();
qemu_irq_raise(s->dev.irq[0]);
qemu_irq_raise(pci_dev->irq[0]);
}
}
} else {
@ -628,7 +637,7 @@ static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
}
iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
pci_dma_sglist_init(&cmd->qsg, &s->dev, 1);
pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
cmd->iov_size = iov_size;
return cmd->iov_size;
@ -655,6 +664,7 @@ static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
{
PCIDevice *pci_dev = PCI_DEVICE(s);
struct mfi_ctrl_info info;
size_t dcmd_size = sizeof(info);
BusChild *kid;
@ -705,11 +715,11 @@ static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
memcpy(info.image_component[0].build_date, __DATE__, 11);
memcpy(info.image_component[0].build_time, __TIME__, 8);
info.image_component_count = 1;
if (s->dev.has_rom) {
if (pci_dev->has_rom) {
uint8_t biosver[32];
uint8_t *ptr;
ptr = memory_region_get_ram_ptr(&s->dev.rom);
ptr = memory_region_get_ram_ptr(&pci_dev->rom);
memcpy(biosver, ptr + 0x41, 31);
memcpy(info.image_component[1].name, "BIOS", 4);
memcpy(info.image_component[1].version, biosver,
@ -1900,6 +1910,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
PCIDevice *pci_dev = PCI_DEVICE(s);
uint64_t frame_addr;
uint32_t frame_count;
int i;
@ -1923,9 +1934,9 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
break;
case MFI_OMSK:
s->intr_mask = val;
if (!megasas_intr_enabled(s) && !msix_enabled(&s->dev)) {
if (!megasas_intr_enabled(s) && !msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
qemu_irq_lower(s->dev.irq[0]);
qemu_irq_lower(pci_dev->irq[0]);
}
if (megasas_intr_enabled(s)) {
trace_megasas_intr_enabled();
@ -1939,9 +1950,9 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
/* Update reply queue pointer */
trace_megasas_qf_update(s->reply_queue_head, s->busy);
stl_le_phys(s->producer_pa, s->reply_queue_head);
if (!msix_enabled(&s->dev)) {
if (!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
qemu_irq_lower(s->dev.irq[0]);
qemu_irq_lower(pci_dev->irq[0]);
}
}
break;
@ -2039,7 +2050,7 @@ static void megasas_soft_reset(MegasasState *s)
static void megasas_scsi_reset(DeviceState *dev)
{
MegasasState *s = DO_UPCAST(MegasasState, dev.qdev, dev);
MegasasState *s = MEGASAS(dev);
megasas_soft_reset(s);
}
@ -2050,7 +2061,7 @@ static const VMStateDescription vmstate_megasas = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, MegasasState),
VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
VMSTATE_INT32(fw_state, MegasasState),
VMSTATE_INT32(intr_mask, MegasasState),
@ -2064,10 +2075,10 @@ static const VMStateDescription vmstate_megasas = {
static void megasas_scsi_uninit(PCIDevice *d)
{
MegasasState *s = DO_UPCAST(MegasasState, dev, d);
MegasasState *s = MEGASAS(d);
#ifdef USE_MSIX
msix_uninit(&s->dev, &s->mmio_io);
msix_uninit(d, &s->mmio_io);
#endif
memory_region_destroy(&s->mmio_io);
memory_region_destroy(&s->port_io);
@ -2087,11 +2098,13 @@ static const struct SCSIBusInfo megasas_scsi_info = {
static int megasas_scsi_init(PCIDevice *dev)
{
MegasasState *s = DO_UPCAST(MegasasState, dev, dev);
DeviceState *d = DEVICE(dev);
MegasasState *s = MEGASAS(dev);
uint8_t *pci_conf;
int i, bar_type;
Error *err = NULL;
pci_conf = s->dev.config;
pci_conf = dev->config;
/* PCI latency timer = 0 */
pci_conf[PCI_LATENCY_TIMER] = 0;
@ -2108,7 +2121,7 @@ static int megasas_scsi_init(PCIDevice *dev)
#ifdef USE_MSIX
/* MSI-X support is currently broken */
if (megasas_use_msix(s) &&
msix_init(&s->dev, 15, &s->mmio_io, 0, 0x2000)) {
msix_init(dev, 15, &s->mmio_io, 0, 0x2000)) {
s->flags &= ~MEGASAS_MASK_USE_MSIX;
}
#else
@ -2116,12 +2129,12 @@ static int megasas_scsi_init(PCIDevice *dev)
#endif
bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
pci_register_bar(&s->dev, 0, bar_type, &s->mmio_io);
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
pci_register_bar(&s->dev, 3, bar_type, &s->queue_io);
pci_register_bar(dev, 0, bar_type, &s->mmio_io);
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
pci_register_bar(dev, 3, bar_type, &s->queue_io);
if (megasas_use_msix(s)) {
msix_vector_use(&s->dev, 0);
msix_vector_use(dev, 0);
}
if (!s->sas_addr) {
@ -2158,8 +2171,14 @@ static int megasas_scsi_init(PCIDevice *dev)
s->frames[i].state = s;
}
scsi_bus_new(&s->bus, &dev->qdev, &megasas_scsi_info, NULL);
scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_new(&s->bus, DEVICE(dev), &megasas_scsi_info, NULL);
if (!d->hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_free(err);
return -1;
}
}
return 0;
}
@ -2198,7 +2217,7 @@ static void megasas_class_init(ObjectClass *oc, void *data)
}
static const TypeInfo megasas_info = {
.name = "megasas",
.name = TYPE_MEGASAS,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(MegasasState),
.class_init = megasas_class_init,

22
hw/scsi/scsi-bus.c
View File

@ -209,10 +209,11 @@ static int scsi_qdev_exit(DeviceState *qdev)
/* handle legacy '-drive if=scsi,...' cmd line args */
SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, BlockDriverState *bdrv,
int unit, bool removable, int bootindex,
const char *serial)
const char *serial, Error **errp)
{
const char *driver;
DeviceState *dev;
Error *err = NULL;
driver = bdrv_is_sg(bdrv) ? "scsi-generic" : "scsi-disk";
dev = qdev_create(&bus->qbus, driver);
@ -227,19 +228,25 @@ SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, BlockDriverState *bdrv,
qdev_prop_set_string(dev, "serial", serial);
}
if (qdev_prop_set_drive(dev, "drive", bdrv) < 0) {
error_setg(errp, "Setting drive property failed");
qdev_free(dev);
return NULL;
}
if (qdev_init(dev) < 0)
object_property_set_bool(OBJECT(dev), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
qdev_free(dev);
return NULL;
}
return SCSI_DEVICE(dev);
}
int scsi_bus_legacy_handle_cmdline(SCSIBus *bus)
void scsi_bus_legacy_handle_cmdline(SCSIBus *bus, Error **errp)
{
Location loc;
DriveInfo *dinfo;
int res = 0, unit;
int unit;
Error *err = NULL;
loc_push_none(&loc);
for (unit = 0; unit <= bus->info->max_target; unit++) {
@ -248,13 +255,14 @@ int scsi_bus_legacy_handle_cmdline(SCSIBus *bus)
continue;
}
qemu_opts_loc_restore(dinfo->opts);
if (!scsi_bus_legacy_add_drive(bus, dinfo->bdrv, unit, false, -1, NULL)) {
res = -1;
scsi_bus_legacy_add_drive(bus, dinfo->bdrv, unit, false, -1, NULL,
&err);
if (err != NULL) {
error_propagate(errp, err);
break;
}
}
loc_pop(&loc);
return res;
}
static int32_t scsi_invalid_field(SCSIRequest *req, uint8_t *buf)

7
hw/scsi/spapr_vscsi.c
View File

@ -912,12 +912,17 @@ static void spapr_vscsi_reset(VIOsPAPRDevice *dev)
static int spapr_vscsi_init(VIOsPAPRDevice *dev)
{
VSCSIState *s = VIO_SPAPR_VSCSI_DEVICE(dev);
Error *err = NULL;
dev->crq.SendFunc = vscsi_do_crq;
scsi_bus_new(&s->bus, &dev->qdev, &vscsi_scsi_info, NULL);
if (!dev->qdev.hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_free(err);
return -1;
}
}
return 0;

7
hw/scsi/virtio-scsi.c
View File

@ -619,6 +619,7 @@ static int virtio_scsi_device_init(VirtIODevice *vdev)
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
VirtIOSCSI *s = VIRTIO_SCSI(vdev);
static int virtio_scsi_id;
Error *err = NULL;
int ret;
ret = virtio_scsi_common_init(vs);
@ -629,7 +630,11 @@ static int virtio_scsi_device_init(VirtIODevice *vdev)
scsi_bus_new(&s->bus, qdev, &virtio_scsi_scsi_info, vdev->bus_name);
if (!qdev->hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus);
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
if (err != NULL) {
error_free(err);
return -1;
}
}
register_savevm(qdev, "virtio-scsi", virtio_scsi_id++, 1,

4
hw/scsi/vmw_pvscsi.c
View File

@ -1136,7 +1136,7 @@ pvscsi_post_load(void *opaque, int version_id)
}
static const VMStateDescription vmstate_pvscsi = {
.name = TYPE_PVSCSI,
.name = "pvscsi",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
@ -1201,7 +1201,7 @@ static void pvscsi_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pvscsi_info = {
.name = "pvscsi",
.name = TYPE_PVSCSI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PVSCSIState),
.class_init = pvscsi_class_init,

51
hw/timer/hpet.c
View File

@ -42,6 +42,9 @@
#define HPET_MSI_SUPPORT 0
#define TYPE_HPET "hpet"
#define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
struct HPETState;
typedef struct HPETTimer { /* timers */
uint8_t tn; /*timer number*/
@ -59,7 +62,10 @@ typedef struct HPETTimer { /* timers */
} HPETTimer;
typedef struct HPETState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint64_t hpet_offset;
qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
@ -634,7 +640,8 @@ static const MemoryRegionOps hpet_ram_ops = {
static void hpet_reset(DeviceState *d)
{
HPETState *s = FROM_SYSBUS(HPETState, SYS_BUS_DEVICE(d));
HPETState *s = HPET(d);
SysBusDevice *sbd = SYS_BUS_DEVICE(d);
int i;
for (i = 0; i < s->num_timers; i++) {
@ -657,7 +664,7 @@ static void hpet_reset(DeviceState *d)
s->hpet_offset = 0ULL;
s->config = 0ULL;
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
hpet_cfg.hpet[s->hpet_id].address = SYS_BUS_DEVICE(d)->mmio[0].addr;
hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr;
/* to document that the RTC lowers its output on reset as well */
s->rtc_irq_level = 0;
@ -665,7 +672,7 @@ static void hpet_reset(DeviceState *d)
static void hpet_handle_legacy_irq(void *opaque, int n, int level)
{
HPETState *s = FROM_SYSBUS(HPETState, opaque);
HPETState *s = HPET(opaque);
if (n == HPET_LEGACY_PIT_INT) {
if (!hpet_in_legacy_mode(s)) {
@ -679,9 +686,20 @@ static void hpet_handle_legacy_irq(void *opaque, int n, int level)
}
}
static int hpet_init(SysBusDevice *dev)
static void hpet_init(Object *obj)
{
HPETState *s = FROM_SYSBUS(HPETState, dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
HPETState *s = HPET(obj);
/* HPET Area */
memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400);
sysbus_init_mmio(sbd, &s->iomem);
}
static void hpet_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
HPETState *s = HPET(dev);
int i;
HPETTimer *timer;
@ -691,14 +709,14 @@ static int hpet_init(SysBusDevice *dev)
}
if (hpet_cfg.count == 8) {
fprintf(stderr, "Only 8 instances of HPET is allowed\n");
return -1;
error_setg(errp, "Only 8 instances of HPET is allowed");
return;
}
s->hpet_id = hpet_cfg.count++;
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
sysbus_init_irq(dev, &s->irqs[i]);
sysbus_init_irq(sbd, &s->irqs[i]);
}
if (s->num_timers < HPET_MIN_TIMERS) {
@ -718,13 +736,8 @@ static int hpet_init(SysBusDevice *dev)
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
s->capability |= ((HPET_CLK_PERIOD) << 32);
qdev_init_gpio_in(&dev->qdev, hpet_handle_legacy_irq, 2);
qdev_init_gpio_out(&dev->qdev, &s->pit_enabled, 1);
/* HPET Area */
memory_region_init_io(&s->iomem, OBJECT(s), &hpet_ram_ops, s, "hpet", 0x400);
sysbus_init_mmio(dev, &s->iomem);
return 0;
qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2);
qdev_init_gpio_out(dev, &s->pit_enabled, 1);
}
static Property hpet_device_properties[] = {
@ -736,9 +749,8 @@ static Property hpet_device_properties[] = {
static void hpet_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = hpet_init;
dc->realize = hpet_realize;
dc->no_user = 1;
dc->reset = hpet_reset;
dc->vmsd = &vmstate_hpet;
@ -746,9 +758,10 @@ static void hpet_device_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo hpet_device_info = {
.name = "hpet",
.name = TYPE_HPET,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(HPETState),
.instance_init = hpet_init,
.class_init = hpet_device_class_init,
};

2
hw/timer/imx_epit.c
View File

@ -370,7 +370,7 @@ static const MemoryRegionOps imx_epit_ops = {
};
static const VMStateDescription vmstate_imx_timer_epit = {
.name = TYPE_IMX_EPIT,
.name = "imx.epit",
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,

2
hw/timer/imx_gpt.c
View File

@ -142,7 +142,7 @@ typedef struct {
} IMXGPTState;
static const VMStateDescription vmstate_imx_timer_gpt = {
.name = TYPE_IMX_GPT,
.name = "imx.gpt",
.version_id = 3,
.minimum_version_id = 3,
.minimum_version_id_old = 3,

2
hw/usb/ccid-card-passthru.c
View File

@ -364,7 +364,7 @@ static int passthru_exitfn(CCIDCardState *base)
}
static VMStateDescription passthru_vmstate = {
.name = PASSTHRU_DEV_NAME,
.name = "ccid-card-passthru",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {

2
hw/usb/dev-smartcard-reader.c
View File

@ -1397,7 +1397,7 @@ static VMStateDescription usb_device_vmstate = {
};
static VMStateDescription ccid_vmstate = {
.name = CCID_DEV_NAME,
.name = "usb-ccid",
.version_id = 1,
.minimum_version_id = 1,
.post_load = ccid_post_load,

4
hw/usb/dev-storage.c
View File

@ -595,6 +595,7 @@ static int usb_msd_initfn_storage(USBDevice *dev)
MSDState *s = DO_UPCAST(MSDState, dev, dev);
BlockDriverState *bs = s->conf.bs;
SCSIDevice *scsi_dev;
Error *err = NULL;
if (!bs) {
error_report("drive property not set");
@ -619,7 +620,8 @@ static int usb_msd_initfn_storage(USBDevice *dev)
usb_desc_init(dev);
scsi_bus_new(&s->bus, &s->dev.qdev, &usb_msd_scsi_info_storage, NULL);
scsi_dev = scsi_bus_legacy_add_drive(&s->bus, bs, 0, !!s->removable,
s->conf.bootindex, dev->serial);
s->conf.bootindex, dev->serial,
&err);
if (!scsi_dev) {
return -1;
}

51
hw/usb/hcd-ohci.c
View File

@ -1843,51 +1843,61 @@ static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
return 0;
}
#define TYPE_PCI_OHCI "pci-ohci"
#define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI)
typedef struct {
PCIDevice pci_dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
OHCIState state;
char *masterbus;
uint32_t num_ports;
uint32_t firstport;
} OHCIPCIState;
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
static int usb_ohci_initfn_pci(PCIDevice *dev)
{
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
OHCIPCIState *ohci = PCI_OHCI(dev);
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
if (usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0,
ohci->masterbus, ohci->firstport,
pci_get_address_space(dev)) != 0) {
return -1;
}
ohci->state.irq = ohci->pci_dev.irq[0];
ohci->state.irq = dev->irq[0];
/* TODO: avoid cast below by using dev */
pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem);
pci_register_bar(dev, 0, 0, &ohci->state.mem);
return 0;
}
#define TYPE_SYSBUS_OHCI "sysbus-ohci"
#define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
OHCIState ohci;
uint32_t num_ports;
dma_addr_t dma_offset;
} OHCISysBusState;
static int ohci_init_pxa(SysBusDevice *dev)
static void ohci_realize_pxa(DeviceState *dev, Error **errp)
{
OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
OHCISysBusState *s = SYSBUS_OHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
/* Cannot fail as we pass NULL for masterbus */
usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0,
usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, NULL, 0,
&address_space_memory);
sysbus_init_irq(dev, &s->ohci.irq);
sysbus_init_mmio(dev, &s->ohci.mem);
return 0;
sysbus_init_irq(sbd, &s->ohci.irq);
sysbus_init_mmio(sbd, &s->ohci.mem);
}
static Property ohci_pci_properties[] = {
@ -1912,7 +1922,7 @@ static void ohci_pci_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo ohci_pci_info = {
.name = "pci-ohci",
.name = TYPE_PCI_OHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(OHCIPCIState),
.class_init = ohci_pci_class_init,
@ -1927,15 +1937,14 @@ static Property ohci_sysbus_properties[] = {
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
sbc->init = ohci_init_pxa;
dc->realize = ohci_realize_pxa;
dc->desc = "OHCI USB Controller";
dc->props = ohci_sysbus_properties;
}
static const TypeInfo ohci_sysbus_info = {
.name = "sysbus-ohci",
.name = TYPE_SYSBUS_OHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OHCISysBusState),
.class_init = ohci_sysbus_class_init,

104
hw/usb/hcd-xhci.c
View File

@ -443,7 +443,10 @@ typedef struct XHCIInterrupter {
} XHCIInterrupter;
struct XHCIState {
PCIDevice pci_dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
USBBus bus;
qemu_irq irq;
MemoryRegion mem;
@ -482,6 +485,11 @@ struct XHCIState {
XHCIRing cmd_ring;
};
#define TYPE_XHCI "nec-usb-xhci"
#define XHCI(obj) \
OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
typedef struct XHCIEvRingSeg {
uint32_t addr_low;
uint32_t addr_high;
@ -654,7 +662,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
assert((len % sizeof(uint32_t)) == 0);
pci_dma_read(&xhci->pci_dev, addr, buf, len);
pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
for (i = 0; i < (len / sizeof(uint32_t)); i++) {
buf[i] = le32_to_cpu(buf[i]);
@ -672,7 +680,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
for (i = 0; i < (len / sizeof(uint32_t)); i++) {
tmp[i] = cpu_to_le32(buf[i]);
}
pci_dma_write(&xhci->pci_dev, addr, tmp, len);
pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
}
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
@ -699,10 +707,11 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
static void xhci_intx_update(XHCIState *xhci)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
int level = 0;
if (msix_enabled(&xhci->pci_dev) ||
msi_enabled(&xhci->pci_dev)) {
if (msix_enabled(pci_dev) ||
msi_enabled(pci_dev)) {
return;
}
@ -718,9 +727,10 @@ static void xhci_intx_update(XHCIState *xhci)
static void xhci_msix_update(XHCIState *xhci, int v)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
bool enabled;
if (!msix_enabled(&xhci->pci_dev)) {
if (!msix_enabled(pci_dev)) {
return;
}
@ -731,17 +741,19 @@ static void xhci_msix_update(XHCIState *xhci, int v)
if (enabled) {
trace_usb_xhci_irq_msix_use(v);
msix_vector_use(&xhci->pci_dev, v);
msix_vector_use(pci_dev, v);
xhci->intr[v].msix_used = true;
} else {
trace_usb_xhci_irq_msix_unuse(v);
msix_vector_unuse(&xhci->pci_dev, v);
msix_vector_unuse(pci_dev, v);
xhci->intr[v].msix_used = false;
}
}
static void xhci_intr_raise(XHCIState *xhci, int v)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
xhci->intr[v].erdp_low |= ERDP_EHB;
xhci->intr[v].iman |= IMAN_IP;
xhci->usbsts |= USBSTS_EINT;
@ -754,15 +766,15 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
return;
}
if (msix_enabled(&xhci->pci_dev)) {
if (msix_enabled(pci_dev)) {
trace_usb_xhci_irq_msix(v);
msix_notify(&xhci->pci_dev, v);
msix_notify(pci_dev, v);
return;
}
if (msi_enabled(&xhci->pci_dev)) {
if (msi_enabled(pci_dev)) {
trace_usb_xhci_irq_msi(v);
msi_notify(&xhci->pci_dev, v);
msi_notify(pci_dev, v);
return;
}
@ -785,6 +797,7 @@ static void xhci_die(XHCIState *xhci)
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCIInterrupter *intr = &xhci->intr[v];
XHCITRB ev_trb;
dma_addr_t addr;
@ -803,7 +816,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
ev_trb.status, ev_trb.control);
addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
intr->er_ep_idx++;
if (intr->er_ep_idx >= intr->er_size) {
@ -950,9 +963,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
dma_addr_t *addr)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
while (1) {
TRBType type;
pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
trb->addr = ring->dequeue;
trb->ccs = ring->ccs;
le64_to_cpus(&trb->parameter);
@ -985,6 +1000,7 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCITRB trb;
int length = 0;
dma_addr_t dequeue = ring->dequeue;
@ -994,7 +1010,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
while (1) {
TRBType type;
pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
le64_to_cpus(&trb.parameter);
le32_to_cpus(&trb.status);
le32_to_cpus(&trb.control);
@ -1046,7 +1062,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
return;
}
dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
le32_to_cpus(&seg.addr_low);
le32_to_cpus(&seg.addr_high);
le32_to_cpus(&seg.size);
@ -1521,7 +1537,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
int i;
xfer->int_req = false;
pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
for (i = 0; i < xfer->trb_count; i++) {
XHCITRB *trb = &xfer->trbs[i];
dma_addr_t addr;
@ -2106,7 +2122,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
assert(slotid >= 1 && slotid <= xhci->numslots);
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid);
poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
ictx = xhci_mask64(pictx);
octx = xhci_mask64(poctx);
@ -2427,7 +2443,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
/* TODO: actually implement real values here */
bw_ctx[0] = 0;
memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
return CC_SUCCESS;
}
@ -2450,11 +2466,12 @@ static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
{
PCIDevice *pci_dev = PCI_DEVICE(xhci);
uint32_t buf[8];
uint32_t obuf[8];
dma_addr_t paddr = xhci_mask64(addr);
pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
pci_dma_read(pci_dev, paddr, &buf, 32);
memcpy(obuf, buf, sizeof(obuf));
@ -2470,7 +2487,7 @@ static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
}
pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
pci_dma_write(pci_dev, paddr, &obuf, 32);
}
static void xhci_process_commands(XHCIState *xhci)
@ -2681,7 +2698,7 @@ static void xhci_port_reset(XHCIPort *port)
static void xhci_reset(DeviceState *dev)
{
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
XHCIState *xhci = XHCI(dev);
int i;
trace_usb_xhci_reset();
@ -2926,6 +2943,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
DeviceState *d = DEVICE(ptr);
trace_usb_xhci_oper_write(reg, val);
@ -2939,7 +2957,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
xhci->usbcmd = val & 0xc0f;
xhci_mfwrap_update(xhci);
if (val & USBCMD_HCRST) {
xhci_reset(&xhci->pci_dev.qdev);
xhci_reset(d);
}
xhci_intx_update(xhci);
break;
@ -3265,8 +3283,9 @@ static USBBusOps xhci_bus_ops = {
.wakeup_endpoint = xhci_wakeup_endpoint,
};
static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
static void usb_xhci_init(XHCIState *xhci)
{
DeviceState *dev = DEVICE(xhci);
XHCIPort *port;
int i, usbports, speedmask;
@ -3281,7 +3300,7 @@ static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
usbports = MAX(xhci->numports_2, xhci->numports_3);
xhci->numports = xhci->numports_2 + xhci->numports_3;
usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
usb_bus_new(&xhci->bus, &xhci_bus_ops, dev);
for (i = 0; i < usbports; i++) {
speedmask = 0;
@ -3313,14 +3332,14 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
{
int i, ret;
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
XHCIState *xhci = XHCI(dev);
xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
xhci->pci_dev.config[0x60] = 0x30; /* release number */
dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
dev->config[0x60] = 0x30; /* release number */
usb_xhci_init(xhci, &dev->qdev);
usb_xhci_init(xhci);
if (xhci->numintrs > MAXINTRS) {
xhci->numintrs = MAXINTRS;
@ -3340,7 +3359,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
xhci->irq = xhci->pci_dev.irq[0];
xhci->irq = dev->irq[0];
memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
@ -3366,18 +3385,18 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
memory_region_add_subregion(&xhci->mem, offset, &port->mem);
}
pci_register_bar(&xhci->pci_dev, 0,
pci_register_bar(dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
&xhci->mem);
ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0);
ret = pcie_endpoint_cap_init(dev, 0xa0);
assert(ret >= 0);
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false);
msi_init(dev, 0x70, xhci->numintrs, true, false);
}
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
msix_init(&xhci->pci_dev, xhci->numintrs,
msix_init(dev, xhci->numintrs,
&xhci->mem, 0, OFF_MSIX_TABLE,
&xhci->mem, 0, OFF_MSIX_PBA,
0x90);
@ -3389,6 +3408,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
static int usb_xhci_post_load(void *opaque, int version_id)
{
XHCIState *xhci = opaque;
PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCISlot *slot;
XHCIEPContext *epctx;
dma_addr_t dcbaap, pctx;
@ -3404,7 +3424,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
continue;
}
slot->ctx =
xhci_mask64(ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid));
xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
slot->uport = xhci_lookup_uport(xhci, slot_ctx);
assert(slot->uport && slot->uport->dev);
@ -3429,9 +3449,9 @@ static int usb_xhci_post_load(void *opaque, int version_id)
for (intr = 0; intr < xhci->numintrs; intr++) {
if (xhci->intr[intr].msix_used) {
msix_vector_use(&xhci->pci_dev, intr);
msix_vector_use(pci_dev, intr);
} else {
msix_vector_unuse(&xhci->pci_dev, intr);
msix_vector_unuse(pci_dev, intr);
}
}
@ -3524,8 +3544,8 @@ static const VMStateDescription vmstate_xhci = {
.version_id = 1,
.post_load = usb_xhci_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(pci_dev, XHCIState),
VMSTATE_MSIX(pci_dev, XHCIState),
VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
VMSTATE_MSIX(parent_obj, XHCIState),
VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
vmstate_xhci_port, XHCIPort),
@ -3581,7 +3601,7 @@ static void xhci_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo xhci_info = {
.name = "nec-usb-xhci",
.name = TYPE_XHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(XHCIState),
.class_init = xhci_class_init,

35
hw/xen/xen_platform.c
View File

@ -49,7 +49,10 @@
#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
typedef struct PCIXenPlatformState {
PCIDevice pci_dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion fixed_io;
MemoryRegion bar;
MemoryRegion mmio_bar;
@ -62,6 +65,10 @@ typedef struct PCIXenPlatformState {
int log_buffer_off;
} PCIXenPlatformState;
#define TYPE_XEN_PLATFORM "xen-platform"
#define XEN_PLATFORM(obj) \
OBJECT_CHECK(PCIXenPlatformState, (obj), TYPE_XEN_PLATFORM)
#define XEN_PLATFORM_IOPORT 0x10
/* Send bytes to syslog */
@ -88,7 +95,7 @@ static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
PCI_CLASS_NETWORK_ETHERNET
&& strcmp(d->name, "xen-pci-passthrough") != 0) {
qdev_free(&d->qdev);
qdev_free(DEVICE(d));
}
}
@ -103,7 +110,7 @@ static void unplug_disks(PCIBus *b, PCIDevice *d, void *o)
if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
PCI_CLASS_STORAGE_IDE
&& strcmp(d->name, "xen-pci-passthrough") != 0) {
qdev_unplug(&(d->qdev), NULL);
qdev_unplug(DEVICE(d), NULL);
}
}
@ -117,7 +124,8 @@ static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t v
PCIXenPlatformState *s = opaque;
switch (addr) {
case 0:
case 0: {
PCIDevice *pci_dev = PCI_DEVICE(s);
/* Unplug devices. Value is a bitmask of which devices to
unplug, with bit 0 the IDE devices, bit 1 the network
devices, and bit 2 the non-primary-master IDE devices. */
@ -125,16 +133,17 @@ static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t v
DPRINTF("unplug disks\n");
bdrv_drain_all();
bdrv_flush_all();
pci_unplug_disks(s->pci_dev.bus);
pci_unplug_disks(pci_dev->bus);
}
if (val & UNPLUG_ALL_NICS) {
DPRINTF("unplug nics\n");
pci_unplug_nics(s->pci_dev.bus);
pci_unplug_nics(pci_dev->bus);
}
if (val & UNPLUG_AUX_IDE_DISKS) {
DPRINTF("unplug auxiliary disks not supported\n");
}
break;
}
case 2:
switch (val) {
case 1:
@ -368,7 +377,7 @@ static const VMStateDescription vmstate_xen_platform = {
.minimum_version_id_old = 4,
.post_load = xen_platform_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
VMSTATE_PCI_DEVICE(parent_obj, PCIXenPlatformState),
VMSTATE_UINT8(flags, PCIXenPlatformState),
VMSTATE_END_OF_LIST()
}
@ -376,10 +385,10 @@ static const VMStateDescription vmstate_xen_platform = {
static int xen_platform_initfn(PCIDevice *dev)
{
PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
PCIXenPlatformState *d = XEN_PLATFORM(dev);
uint8_t *pci_conf;
pci_conf = d->pci_dev.config;
pci_conf = dev->config;
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
@ -388,11 +397,11 @@ static int xen_platform_initfn(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 1;
platform_ioport_bar_setup(d);
pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
/* reserve 16MB mmio address for share memory*/
platform_mmio_setup(d);
pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
&d->mmio_bar);
platform_fixed_ioport_init(d);
@ -402,7 +411,7 @@ static int xen_platform_initfn(PCIDevice *dev)
static void platform_reset(DeviceState *dev)
{
PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);
PCIXenPlatformState *s = XEN_PLATFORM(dev);
platform_fixed_ioport_reset(s);
}
@ -425,7 +434,7 @@ static void xen_platform_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo xen_platform_info = {
.name = "xen-platform",
.name = TYPE_XEN_PLATFORM,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIXenPlatformState),
.class_init = xen_platform_class_init,

10
include/hw/pci-host/q35.h
View File

@ -43,7 +43,10 @@
OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
typedef struct MCHPCIState {
PCIDevice d;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
MemoryRegion *ram_memory;
MemoryRegion *pci_address_space;
MemoryRegion *system_memory;
@ -59,7 +62,10 @@ typedef struct MCHPCIState {
} MCHPCIState;
typedef struct Q35PCIHost {
PCIExpressHost host;
/*< private >*/
PCIExpressHost parent_obj;
/*< public >*/
MCHPCIState mch;
} Q35PCIHost;

4
include/hw/scsi/scsi.h
View File

@ -162,8 +162,8 @@ static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, BlockDriverState *bdrv,
int unit, bool removable, int bootindex,
const char *serial);
int scsi_bus_legacy_handle_cmdline(SCSIBus *bus);
const char *serial, Error **errp);
void scsi_bus_legacy_handle_cmdline(SCSIBus *bus, Error **errp);
/*
* Predefined sense codes

12
include/hw/sysbus.h
View File

@ -23,8 +23,20 @@ typedef struct SysBusDevice SysBusDevice;
#define SYS_BUS_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(SysBusDeviceClass, (obj), TYPE_SYS_BUS_DEVICE)
/**
* SysBusDeviceClass:
* @init: Callback function invoked when the #DeviceState.realized property
* is changed to %true. Deprecated, new types inheriting directly from
* TYPE_SYS_BUS_DEVICE should use #DeviceClass.realize instead, new leaf
* types should consult their respective parent type.
*
* SysBusDeviceClass is not overriding #DeviceClass.realize, so derived
* classes overriding it are not required to invoke its implementation.
*/
typedef struct SysBusDeviceClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
int (*init)(SysBusDevice *dev);
} SysBusDeviceClass;