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Queued target/s390x patches 

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Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170623' into staging

Queued target/s390x patches

# gpg: Signature made Fri 23 Jun 2017 17:18:24 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170623:
  target/s390x: Implement idte instruction
  target/s390x: Improve heuristic for ipte
  target/s390x: Indicate and check for local tlb clearing
  target/s390x: Clean up TB flag bits
  target/s390x: Finish implementing ETF2-ENH
  target/s390x: Mark STFLE_49 facility as available
  target/s390x: Implement processor-assist insn
  target/s390x: Implement execution-hint insns
  target/s390x: Mark STFLE_53 facility as available
  target/s390x: Implement load-and-zero-rightmost-byte insns
  target/s390x: Implement load-on-condition-2 insns
  target/s390x: Mark FPSEH facility as available
  target/s390x: implement mvcos instruction
  target/s390x: change PSW_SHIFT_KEY
  target/s390x: Map existing FAC_* names to S390_FEAT_* names

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-06-23 18:11:48 +01:00
parent 14a7fe1a26 be7f28de5d
commit 931892e8a6
7 changed files with 411 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
target/s390x/cpu.h
View File

@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#undef PSW_MASK_WAIT
#undef PSW_MASK_PSTATE
#undef PSW_MASK_ASC
#undef PSW_SHIFT_ASC
#undef PSW_MASK_CC
#undef PSW_MASK_PM
#undef PSW_MASK_64
@ -315,11 +316,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
#define PSW_MASK_KEY 0x00F0000000000000ULL
#define PSW_SHIFT_KEY 56
#define PSW_SHIFT_KEY 52
#define PSW_MASK_MCHECK 0x0004000000000000ULL
#define PSW_MASK_WAIT 0x0002000000000000ULL
#define PSW_MASK_PSTATE 0x0001000000000000ULL
#define PSW_MASK_ASC 0x0000C00000000000ULL
#define PSW_SHIFT_ASC 46
#define PSW_MASK_CC 0x0000300000000000ULL
#define PSW_MASK_PM 0x00000F0000000000ULL
#define PSW_MASK_64 0x0000000100000000ULL
@ -336,24 +338,26 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_ASC_SECONDARY 0x0000800000000000ULL
#define PSW_ASC_HOME 0x0000C00000000000ULL
/* the address space values shifted */
#define AS_PRIMARY 0
#define AS_ACCREG 1
#define AS_SECONDARY 2
#define AS_HOME 3
/* tb flags */
#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
#define FLAG_MASK_32 0x00001000
#define FLAG_MASK_PSW_SHIFT 31
#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
#define CR0_SECONDARY 0x0000000004000000ULL
#define CR0_EDAT 0x0000000000800000ULL
/* MMU */
@ -361,7 +365,18 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define MMU_SECONDARY_IDX 1
#define MMU_HOME_IDX 2
static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
{
uint16_t pkm = env->cregs[3] >> 16;
if (env->psw.mask & PSW_MASK_PSTATE) {
/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
return pkm & (0x80 >> psw_key);
}
return true;
}
static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
{
switch (env->psw.mask & PSW_MASK_ASC) {
case PSW_ASC_PRIMARY:
@ -396,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
{
*pc = env->psw.addr;
*cs_base = env->ex_value;
*flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
}
#define MAX_ILEN 6

6
target/s390x/cpu_models.c
View File

@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel *max_model,
static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
{
static const int feats[] = {
S390_FEAT_DAT_ENH,
S390_FEAT_STFLE,
S390_FEAT_EXTENDED_IMMEDIATE,
S390_FEAT_EXTENDED_TRANSLATION_2,
@ -682,9 +683,14 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_LONG_DISPLACEMENT_FAST,
S390_FEAT_ETF2_ENH,
S390_FEAT_STORE_CLOCK_FAST,
S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
S390_FEAT_EXECUTE_EXT,
S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
S390_FEAT_STFLE_45,
S390_FEAT_STFLE_49,
S390_FEAT_LOCAL_TLB_CLEARING,
S390_FEAT_STFLE_53,
};
int i;

2
target/s390x/helper.h
View File

@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_2(stfle, i32, env, i64)
DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
@ -130,6 +131,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64)
DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)
DEF_HELPER_4(sigp, i32, env, i64, i32, i64)
DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env)

30
target/s390x/insn-data.def
View File

@ -134,6 +134,15 @@
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
/* BRANCH PREDICTION PRELOAD */
/* ??? Format is SMI, but implemented as NOP, so we need no fields. */
C(0xc700, BPP, E, EH, 0, 0, 0, 0, 0, 0)
/* BRANCH PREDICTION RELATIVE PRELOAD */
/* ??? Format is MII, but implemented as NOP, so we need no fields. */
C(0xc500, BPRP, E, EH, 0, 0, 0, 0, 0, 0)
/* NEXT INSTRUCTION ACCESS INTENT */
/* ??? Format is IE, but implemented as NOP, so we need no fields. */
C(0xb2fa, NIAI, E, EH, 0, 0, 0, 0, 0, 0)
/* CHECKSUM */
C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0)
@ -427,6 +436,11 @@
/* LOAD AND TRAP */
C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
/* LOAD AND ZERO RIGHTMOST BYTE */
C(0xe3eb, LZRF, RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)
C(0xe32a, LZRG, RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)
/* LOAD LOGICAL AND ZERO RIGHTMOST BYTE */
C(0xe33a, LLZRGF, RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)
/* LOAD BYTE */
C(0xb926, LBR, RRE, EI, 0, r2_8s, 0, r1_32, mov2, 0)
C(0xb906, LGBR, RRE, EI, 0, r2_8s, 0, r1, mov2, 0)
@ -514,6 +528,13 @@
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
/* LOAD HALFWORD IMMEDIATE ON CONDITION */
C(0xec42, LOCHI, RIE_g, LOC2, r1, i2, new, r1_32, loc, 0)
C(0xec46, LOCGHI, RIE_g, LOC2, r1, i2, r1, 0, loc, 0)
C(0xec4e, LOCHHI, RIE_g, LOC2, r1_sr32, i2, new, r1_32h, loc, 0)
/* LOAD HIGH ON CONDITION */
C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2, new, r1_32h, loc, 0)
C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0)
/* LOAD PAIR DISJOINT */
D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)
D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ)
@ -590,6 +611,8 @@
C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0)
/* MOVE STRING */
C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0)
/* MOVE WITH OPTIONAL SPECIFICATION */
C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0)
/* MOVE WITH OFFSET */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
@ -676,6 +699,9 @@
/* Implemented as nops of course. */
C(0xe336, PFD, RXY_b, GIE, 0, 0, 0, 0, 0, 0)
C(0xc602, PFDRL, RIL_c, GIE, 0, 0, 0, 0, 0, 0)
/* PERFORM PROCESSOR ASSIST */
/* Implemented as nop of course. */
C(0xb2e8, PPA, RRF_c, PPA, 0, 0, 0, 0, 0, 0)
/* POPULATION COUNT */
C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64)
@ -777,6 +803,8 @@
/* STORE ON CONDITION */
D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
/* STORE HIGH ON CONDITION */
D(0xebe1, STOCFH, RSY_b, LOC2, 0, 0, 0, 0, soc, 0, 2)
/* STORE REVERSED */
C(0xe33f, STRVH, RXY_a, Z, la2, r1_16u, new, m1_16, rev16, 0)
C(0xe33e, STRV, RXY_a, Z, la2, r1_32u, new, m1_32, rev32, 0)
@ -900,6 +928,8 @@
C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0)
/* INSERT STORAGE KEY EXTENDED */
C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0)
/* INVALIDATE DAT TABLE ENTRY */
C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0)
/* INVALIDATE PAGE TABLE ENTRY */
C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0)
/* LOAD CONTROL */

1
target/s390x/insn-format.def
View File

@ -11,6 +11,7 @@ F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
F2(RIL_a, R(1, 8), I(2,16,32))
F2(RIL_b, R(1, 8), I(2,16,32))
F2(RIL_c, M(1, 8), I(2,16,32))

270
target/s390x/mem_helper.c
View File

@ -110,6 +110,20 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr,
}
}
static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
{
if (!(env->psw.mask & PSW_MASK_64)) {
if (!(env->psw.mask & PSW_MASK_32)) {
/* 24-Bit mode */
a &= 0x00ffffff;
} else {
/* 31-Bit mode */
a &= 0x7fffffff;
}
}
return a;
}
static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
uint32_t l, uintptr_t ra)
{
@ -133,6 +147,68 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
}
}
#ifndef CONFIG_USER_ONLY
static void fast_memmove_idx(CPUS390XState *env, uint64_t dest, uint64_t src,
uint32_t len, int dest_idx, int src_idx,
uintptr_t ra)
{
TCGMemOpIdx oi_dest = make_memop_idx(MO_UB, dest_idx);
TCGMemOpIdx oi_src = make_memop_idx(MO_UB, src_idx);
uint32_t len_adj;
void *src_p;
void *dest_p;
uint8_t x;
while (len > 0) {
src = wrap_address(env, src);
dest = wrap_address(env, dest);
src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, src_idx);
dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, dest_idx);
if (src_p && dest_p) {
/* Access to both whole pages granted. */
len_adj = adj_len_to_page(adj_len_to_page(len, src), dest);
memmove(dest_p, src_p, len_adj);
} else {
/* We failed to get access to one or both whole pages. The next
read or write access will likely fill the QEMU TLB for the
next iteration. */
len_adj = 1;
x = helper_ret_ldub_mmu(env, src, oi_src, ra);
helper_ret_stb_mmu(env, dest, x, oi_dest, ra);
}
src += len_adj;
dest += len_adj;
len -= len_adj;
}
}
static int mmu_idx_from_as(uint8_t as)
{
switch (as) {
case AS_PRIMARY:
return MMU_PRIMARY_IDX;
case AS_SECONDARY:
return MMU_SECONDARY_IDX;
case AS_HOME:
return MMU_HOME_IDX;
default:
/* FIXME AS_ACCREG */
g_assert_not_reached();
}
}
static void fast_memmove_as(CPUS390XState *env, uint64_t dest, uint64_t src,
uint32_t len, uint8_t dest_as, uint8_t src_as,
uintptr_t ra)
{
int src_idx = mmu_idx_from_as(src_as);
int dest_idx = mmu_idx_from_as(dest_as);
fast_memmove_idx(env, dest, src, len, dest_idx, src_idx, ra);
}
#endif
static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
uint32_t l, uintptr_t ra)
{
@ -408,20 +484,6 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
return cc;
}
static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
{
if (!(env->psw.mask & PSW_MASK_64)) {
if (!(env->psw.mask & PSW_MASK_32)) {
/* 24-Bit mode */
a &= 0x00ffffff;
} else {
/* 31-Bit mode */
a &= 0x7fffffff;
}
}
return a;
}
static inline uint64_t get_address(CPUS390XState *env, int reg)
{
return wrap_address(env, env->regs[reg]);
@ -1203,13 +1265,22 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
uintptr_t ra = GETPC();
int dsize = (sizes & 1) ? 1 : 2;
int ssize = (sizes & 2) ? 1 : 2;
uint64_t tbl = get_address(env, 1) & ~7;
uint64_t tbl = get_address(env, 1);
uint64_t dst = get_address(env, r1);
uint64_t len = get_length(env, r1 + 1);
uint64_t src = get_address(env, r2);
uint32_t cc = 3;
int i;
/* The lower address bits of TBL are ignored. For TROO, TROT, it's
the low 3 bits (double-word aligned). For TRTO, TRTT, it's either
the low 12 bits (4K, without ETF2-ENH) or 3 bits (with ETF2-ENH). */
if (ssize == 2 && !s390_has_feat(S390_FEAT_ETF2_ENH)) {
tbl &= -4096;
} else {
tbl &= -8;
}
check_alignment(env, len, ssize, ra);
/* Lest we fail to service interrupts in a timely manner, */
@ -1539,6 +1610,57 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
return cc;
}
void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
{
CPUState *cs = CPU(s390_env_get_cpu(env));
const uintptr_t ra = GETPC();
uint64_t table, entry, raddr;
uint16_t entries, i, index = 0;
if (r2 & 0xff000) {
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_SPECIFICATION, 4);
}
if (!(r2 & 0x800)) {
/* invalidation-and-clearing operation */
table = r1 & _ASCE_ORIGIN;
entries = (r2 & 0x7ff) + 1;
switch (r1 & _ASCE_TYPE_MASK) {
case _ASCE_TYPE_REGION1:
index = (r2 >> 53) & 0x7ff;
break;
case _ASCE_TYPE_REGION2:
index = (r2 >> 42) & 0x7ff;
break;
case _ASCE_TYPE_REGION3:
index = (r2 >> 31) & 0x7ff;
break;
case _ASCE_TYPE_SEGMENT:
index = (r2 >> 20) & 0x7ff;
break;
}
for (i = 0; i < entries; i++) {
/* addresses are not wrapped in 24/31bit mode but table index is */
raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
entry = ldq_phys(cs->as, raddr);
if (!(entry & _REGION_ENTRY_INV)) {
/* we are allowed to not store if already invalid */
entry |= _REGION_ENTRY_INV;
stq_phys(cs->as, raddr, entry);
}
}
}
/* We simply flush the complete tlb, therefore we can ignore r3. */
if (m4 & 1) {
tlb_flush(cs);
} else {
tlb_flush_all_cpus_synced(cs);
}
}
/* invalidate pte */
void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
uint32_t m4)
@ -1558,19 +1680,24 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
/* XXX: the LC bit should be considered as 0 if the local-TLB-clearing
facility is not installed. */
if (m4 & 1) {
tlb_flush_page(cs, page);
if (vaddr & ~VADDR_PX) {
tlb_flush_page(cs, page);
/* XXX 31-bit hack */
tlb_flush_page(cs, page ^ 0x80000000);
} else {
/* looks like we don't have a valid virtual address */
tlb_flush(cs);
}
} else {
tlb_flush_page_all_cpus_synced(cs, page);
}
/* XXX 31-bit hack */
if (m4 & 1) {
tlb_flush_page(cs, page ^ 0x80000000);
} else {
tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
if (vaddr & ~VADDR_PX) {
tlb_flush_page_all_cpus_synced(cs, page);
/* XXX 31-bit hack */
tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
} else {
/* looks like we don't have a valid virtual address */
tlb_flush_all_cpus_synced(cs);
}
}
}
@ -1789,3 +1916,94 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
that requires such execution. */
env->ex_value = insn | ilen;
}
uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
uint64_t len)
{
const uint8_t psw_key = (env->psw.mask & PSW_MASK_KEY) >> PSW_SHIFT_KEY;
const uint8_t psw_as = (env->psw.mask & PSW_MASK_ASC) >> PSW_SHIFT_ASC;
const uint64_t r0 = env->regs[0];
const uintptr_t ra = GETPC();
CPUState *cs = CPU(s390_env_get_cpu(env));
uint8_t dest_key, dest_as, dest_k, dest_a;
uint8_t src_key, src_as, src_k, src_a;
uint64_t val;
int cc = 0;
HELPER_LOG("%s dest %" PRIx64 ", src %" PRIx64 ", len %" PRIx64 "\n",
__func__, dest, src, len);
if (!(env->psw.mask & PSW_MASK_DAT)) {
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_SPECIAL_OP, 6);
}
/* OAC (operand access control) for the first operand -> dest */
val = (r0 & 0xffff0000ULL) >> 16;
dest_key = (val >> 12) & 0xf;
dest_as = (val >> 6) & 0x3;
dest_k = (val >> 1) & 0x1;
dest_a = val & 0x1;
/* OAC (operand access control) for the second operand -> src */
val = (r0 & 0x0000ffffULL);
src_key = (val >> 12) & 0xf;
src_as = (val >> 6) & 0x3;
src_k = (val >> 1) & 0x1;
src_a = val & 0x1;
if (!dest_k) {
dest_key = psw_key;
}
if (!src_k) {
src_key = psw_key;
}
if (!dest_a) {
dest_as = psw_as;
}
if (!src_a) {
src_as = psw_as;
}
if (dest_a && dest_as == AS_HOME && (env->psw.mask & PSW_MASK_PSTATE)) {
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_SPECIAL_OP, 6);
}
if (!(env->cregs[0] & CR0_SECONDARY) &&
(dest_as == AS_SECONDARY || src_as == AS_SECONDARY)) {
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_SPECIAL_OP, 6);
}
if (!psw_key_valid(env, dest_key) || !psw_key_valid(env, src_key)) {
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_PRIVILEGED, 6);
}
len = wrap_length(env, len);
if (len > 4096) {
cc = 3;
len = 4096;
}
/* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */
if (src_as == AS_ACCREG || dest_as == AS_ACCREG ||
(env->psw.mask & PSW_MASK_PSTATE)) {
qemu_log_mask(LOG_UNIMP, "%s: AR-mode and PSTATE support missing\n",
__func__);
cpu_restore_state(cs, ra);
program_interrupt(env, PGM_ADDRESSING, 6);
}
/* FIXME: a) LAP
* b) Access using correct keys
* c) AR-mode
*/
#ifdef CONFIG_USER_ONLY
/* psw keys are never valid in user mode, we will never reach this */
g_assert_not_reached();
#else
fast_memmove_as(env, dest, src, len, dest_as, src_as, ra);
#endif
return cc;
}

143
target/s390x/translate.c
View File

@ -323,11 +323,11 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
static int get_mem_index(DisasContext *s)
{
switch (s->tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> 32:
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
return 0;
case PSW_ASC_SECONDARY >> 32:
case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
return 1;
case PSW_ASC_HOME >> 32:
case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
return 2;
default:
tcg_abort();
@ -387,7 +387,7 @@ static inline void gen_trap(DisasContext *s)
#ifndef CONFIG_USER_ONLY
static void check_privileged(DisasContext *s)
{
if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
if (s->tb->flags & FLAG_MASK_PSTATE) {
gen_program_exception(s, PGM_PRIVILEGED);
}
}
@ -1180,39 +1180,10 @@ typedef enum {
EXIT_NORETURN,
} ExitStatus;
typedef enum DisasFacility {
FAC_Z, /* zarch (default) */
FAC_CASS, /* compare and swap and store */
FAC_CASS2, /* compare and swap and store 2*/
FAC_DFP, /* decimal floating point */
FAC_DFPR, /* decimal floating point rounding */
FAC_DO, /* distinct operands */
FAC_EE, /* execute extensions */
FAC_EI, /* extended immediate */
FAC_FPE, /* floating point extension */
FAC_FPSSH, /* floating point support sign handling */
FAC_FPRGR, /* FPR-GR transfer */
FAC_GIE, /* general instructions extension */
FAC_HFP_MA, /* HFP multiply-and-add/subtract */
FAC_HW, /* high-word */
FAC_IEEEE_SIM, /* IEEE exception sumilation */
FAC_MIE, /* miscellaneous-instruction-extensions */
FAC_LAT, /* load-and-trap */
FAC_LOC, /* load/store on condition */
FAC_LD, /* long displacement */
FAC_PC, /* population count */
FAC_SCF, /* store clock fast */
FAC_SFLE, /* store facility list extended */
FAC_ILA, /* interlocked access facility 1 */
FAC_LPP, /* load-program-parameter */
FAC_DAT_ENH, /* DAT-enhancement */
FAC_E2, /* extended-translation facility 2 */
} DisasFacility;
struct DisasInsn {
unsigned opc:16;
DisasFormat fmt:8;
DisasFacility fac:8;
unsigned fac:8;
unsigned spec:8;
const char *name;
@ -2409,12 +2380,31 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
}
#ifndef CONFIG_USER_ONLY
static ExitStatus op_idte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
check_privileged(s);
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
m4 = tcg_const_i32(get_field(s->fields, m4));
} else {
m4 = tcg_const_i32(0);
}
gen_helper_idte(cpu_env, o->in1, o->in2, m4);
tcg_temp_free_i32(m4);
return NO_EXIT;
}
static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
check_privileged(s);
m4 = tcg_const_i32(get_field(s->fields, m4));
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
m4 = tcg_const_i32(get_field(s->fields, m4));
} else {
m4 = tcg_const_i32(0);
}
gen_helper_ipte(cpu_env, o->in1, o->in2, m4);
tcg_temp_free_i32(m4);
return NO_EXIT;
@ -2935,6 +2925,12 @@ static ExitStatus op_lurag(DisasContext *s, DisasOps *o)
}
#endif
static ExitStatus op_lzrb(DisasContext *s, DisasOps *o)
{
tcg_gen_andi_i64(o->out, o->in2, -256);
return NO_EXIT;
}
static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
@ -2955,20 +2951,20 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> 32:
case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 0);
break;
case PSW_ASC_ACCREG >> 32:
case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 1);
break;
case PSW_ASC_SECONDARY >> 32:
case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
if (b2) {
tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
case PSW_ASC_HOME >> 32:
case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 2);
break;
}
@ -3070,6 +3066,14 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
static ExitStatus op_mvcos(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s->fields, r3);
gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
set_cc_static(s);
return NO_EXIT;
}
#ifndef CONFIG_USER_ONLY
static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
{
@ -3662,7 +3666,7 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
static ExitStatus op_soc(DisasContext *s, DisasOps *o)
{
DisasCompare c;
TCGv_i64 a;
TCGv_i64 a, h;
TCGLabel *lab;
int r1;
@ -3682,10 +3686,21 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
r1 = get_field(s->fields, r1);
a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
if (s->insn->data) {
switch (s->insn->data) {
case 1: /* STOCG */
tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
} else {
break;
case 0: /* STOC */
tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
break;
case 2: /* STOCFH */
h = tcg_temp_new_i64();
tcg_gen_shri_i64(h, regs[r1], 32);
tcg_gen_qemu_st32(h, a, get_mem_index(s));
tcg_temp_free_i64(h);
break;
default:
g_assert_not_reached();
}
tcg_temp_free_i64(a);
@ -3782,7 +3797,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
return NO_EXIT;
}
@ -4360,8 +4375,9 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
TCGv_i32 tst = tcg_temp_new_i32();
int m3 = get_field(s->fields, m3);
/* XXX: the C bit in M3 should be considered as 0 when the
ETF2-enhancement facility is not installed. */
if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
m3 = 0;
}
if (m3 & 1) {
tcg_gen_movi_i32(tst, -1);
} else {
@ -5418,6 +5434,39 @@ enum DisasInsnEnum {
#define SPEC_prep_0 0
#define SPEC_wout_0 0
/* Give smaller names to the various facilities. */
#define FAC_Z S390_FEAT_ZARCH
#define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
#define FAC_CASS2 S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2
#define FAC_DFP S390_FEAT_DFP
#define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* DFP-rounding */
#define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
#define FAC_EE S390_FEAT_EXECUTE_EXT
#define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
#define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
#define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPS-sign-handling */
#define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPR-GR-transfer */
#define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
#define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
#define FAC_HW S390_FEAT_STFLE_45 /* high-word */
#define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* IEEE-exception-simulation */
#define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
#define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
#define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
#define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
#define FAC_LD S390_FEAT_LONG_DISPLACEMENT
#define FAC_PC S390_FEAT_STFLE_45 /* population count */
#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
#define FAC_SFLE S390_FEAT_STFLE
#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
#define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
#define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
#define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
#define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
static const DisasInsn insn_info[] = {
#include "insn-data.def"
};
@ -5529,7 +5578,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
case 0x80: /* S */
case 0x82: /* S */
case 0x93: /* S */
case 0xb2: /* S, RRF, RRE */
case 0xb2: /* S, RRF, RRE, IE */
case 0xb3: /* RRE, RRD, RRF */
case 0xb9: /* RRE, RRF */
case 0xe5: /* SSE, SIL */
@ -5545,6 +5594,8 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
case 0xcc: /* RIL */
op2 = (insn << 12) >> 60;
break;
case 0xc5: /* MII */
case 0xc7: /* SMI */
case 0xd0 ... 0xdf: /* SS */
case 0xe1: /* SS */
case 0xe2: /* SS */