From 92fb92d3e9c67f83cbbca0e2b9ca2d88fefd6643 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Sep 2021 08:47:51 -0300 Subject: [PATCH] target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l] PowerISA v3.0B made tlbie[l] hypervisor privileged when PSR=0 and HR=1. To allow the check at translation time, we'll use the HR bit of LPCR to check the MMU mode instead of the PATE.HR. Signed-off-by: Matheus Ferst Message-Id: <20210917114751.206845-3-matheus.ferst@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza Signed-off-by: David Gibson --- target/ppc/translate.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9af1624ad2..b985e9e55b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5517,7 +5517,15 @@ static void gen_tlbiel(DisasContext *ctx) #if defined(CONFIG_USER_ONLY) GEN_PRIV; #else - CHK_SV; + bool psr = (ctx->opcode >> 17) & 0x1; + + if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { + /* + * tlbiel is privileged except when PSR=0 and HR=1, making it + * hypervisor privileged. + */ + GEN_PRIV; + } gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ @@ -5529,12 +5537,20 @@ static void gen_tlbie(DisasContext *ctx) #if defined(CONFIG_USER_ONLY) GEN_PRIV; #else + bool psr = (ctx->opcode >> 17) & 0x1; TCGv_i32 t1; - if (ctx->gtse) { - CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ - } else { - CHK_HV; /* Else hypervisor privileged */ + if (ctx->pr) { + /* tlbie is privileged... */ + GEN_PRIV; + } else if (!ctx->hv) { + if (!ctx->gtse || (!psr && ctx->hr)) { + /* + * ... except when GTSE=0 or when PSR=0 and HR=1, making it + * hypervisor privileged. + */ + GEN_PRIV; + } } if (NARROW_MODE(ctx)) {