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target/microblaze: Remove last of old decoder
All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Remove microblaze-decode.h. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
parent
52065d8f46
commit
921afa9dae
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@ -1,59 +0,0 @@
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/*
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* MicroBlaze insn decoding macros.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_MICROBLAZE_MICROBLAZE_DECODE_H
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#define TARGET_MICROBLAZE_MICROBLAZE_DECODE_H
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/* Convenient binary macros. */
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#define HEX__(n) 0x##n##LU
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#define B8__(x) ((x&0x0000000FLU)?1:0) \
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+ ((x&0x000000F0LU)?2:0) \
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+ ((x&0x00000F00LU)?4:0) \
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+ ((x&0x0000F000LU)?8:0) \
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+ ((x&0x000F0000LU)?16:0) \
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+ ((x&0x00F00000LU)?32:0) \
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+ ((x&0x0F000000LU)?64:0) \
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+ ((x&0xF0000000LU)?128:0)
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#define B8(d) ((unsigned char)B8__(HEX__(d)))
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/* Decode logic, value and mask. */
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#define DEC_ADD {B8(00000000), B8(00110001)}
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#define DEC_SUB {B8(00000001), B8(00110001)}
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#define DEC_AND {B8(00100001), B8(00110101)}
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#define DEC_XOR {B8(00100010), B8(00110111)}
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#define DEC_OR {B8(00100000), B8(00110111)}
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#define DEC_BIT {B8(00100100), B8(00111111)}
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#define DEC_MSR {B8(00100101), B8(00111111)}
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#define DEC_BARREL {B8(00010001), B8(00110111)}
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#define DEC_MUL {B8(00010000), B8(00110111)}
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#define DEC_DIV {B8(00010010), B8(00110111)}
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#define DEC_FPU {B8(00010110), B8(00111111)}
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#define DEC_LD {B8(00110000), B8(00110100)}
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#define DEC_ST {B8(00110100), B8(00110100)}
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#define DEC_IMM {B8(00101100), B8(00111111)}
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#define DEC_BR {B8(00100110), B8(00110111)}
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#define DEC_BCC {B8(00100111), B8(00110111)}
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#define DEC_RTS {B8(00101101), B8(00111111)}
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#define DEC_STREAM {B8(00010011), B8(00110111)}
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#endif
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@ -24,7 +24,6 @@
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#include "exec/exec-all.h"
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#include "tcg/tcg-op.h"
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#include "exec/helper-proto.h"
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#include "microblaze-decode.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-gen.h"
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#include "exec/translator.h"
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@ -65,13 +64,7 @@ typedef struct DisasContext {
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bool r0_set;
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/* Decoder. */
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int type_b;
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uint32_t ir;
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uint32_t ext_imm;
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uint8_t opcode;
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uint8_t rd, ra, rb;
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uint16_t imm;
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unsigned int cpustate_changed;
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unsigned int tb_flags;
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unsigned int tb_flags_to_set;
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@ -82,8 +75,6 @@ typedef struct DisasContext {
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/* Immediate branch-taken destination, or -1 for indirect. */
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uint32_t jmp_dest;
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int abort_at_next_insn;
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} DisasContext;
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static int typeb_imm(DisasContext *dc, int x)
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@ -184,21 +175,6 @@ static bool trap_userspace(DisasContext *dc, bool cond)
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return cond_user;
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}
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static int32_t dec_alu_typeb_imm(DisasContext *dc)
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{
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tcg_debug_assert(dc->type_b);
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return typeb_imm(dc, (int16_t)dc->imm);
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}
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static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
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{
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if (dc->type_b) {
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tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc));
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return &cpu_imm;
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}
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return &cpu_R[dc->rb];
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}
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static TCGv_i32 reg_for_read(DisasContext *dc, int reg)
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{
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if (likely(reg != 0)) {
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@ -1549,16 +1525,6 @@ static void do_rte(DisasContext *dc)
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dc->tb_flags &= ~DRTE_FLAG;
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}
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static void dec_null(DisasContext *dc)
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{
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if (trap_illegal(dc, true)) {
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return;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n",
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(uint32_t)dc->base.pc_next, dc->opcode);
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dc->abort_at_next_insn = 1;
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}
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/* Insns connected to FSL or AXI stream attached devices. */
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static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl)
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{
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@ -1624,40 +1590,6 @@ static bool trans_putd(DisasContext *dc, arg_putd *arg)
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return do_put(dc, arg->ra, arg->rb, 0, arg->ctrl);
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}
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static struct decoder_info {
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struct {
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uint32_t bits;
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uint32_t mask;
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};
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void (*dec)(DisasContext *dc);
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} decinfo[] = {
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{{0, 0}, dec_null}
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};
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static void old_decode(DisasContext *dc, uint32_t ir)
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{
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int i;
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dc->ir = ir;
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/* bit 2 seems to indicate insn type. */
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dc->type_b = ir & (1 << 29);
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dc->opcode = EXTRACT_FIELD(ir, 26, 31);
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dc->rd = EXTRACT_FIELD(ir, 21, 25);
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dc->ra = EXTRACT_FIELD(ir, 16, 20);
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dc->rb = EXTRACT_FIELD(ir, 11, 15);
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dc->imm = EXTRACT_FIELD(ir, 0, 15);
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/* Large switch for all insns. */
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for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
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if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
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decinfo[i].dec(dc);
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break;
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}
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}
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}
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static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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@ -1667,7 +1599,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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dc->cpu = cpu;
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dc->tb_flags = dc->base.tb->flags;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->ext_imm = dc->base.tb->cs_base;
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dc->r0 = NULL;
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dc->r0_set = false;
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@ -1724,7 +1655,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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ir = cpu_ldl_code(env, dc->base.pc_next);
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if (!decode(dc, ir)) {
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old_decode(dc, ir);
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trap_illegal(dc, true);
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}
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if (dc->r0) {
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@ -1764,8 +1695,6 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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assert(!dc->abort_at_next_insn);
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if (dc->base.is_jmp == DISAS_NORETURN) {
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/* We have already exited the TB. */
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return;
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