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target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases 

These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
been added commit 3c824109da ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon. The cases fall back to the default which generates a RESERVED
INSTRUCTION, so it is safe to remove them.
Functionally speaking, the patch is a no-op.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-05-29 16:55:07 +02:00
parent 9f47eb54b2
commit 916e957070
1 changed files with 0 additions and 6 deletions
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6
target/mips/tcg/translate.c
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@ -14076,8 +14076,6 @@ enum {
BGEZALS = 0x13, BGEZALS = 0x13,
BC2F = 0x14, BC2F = 0x14,
BC2T = 0x15, BC2T = 0x15,
BPOSGE64 = 0x1a,
BPOSGE32 = 0x1b,
/* These overlap and are distinguished by bit16 of the instruction */ /* These overlap and are distinguished by bit16 of the instruction */
BC1F = 0x1c, BC1F = 0x1c,
BC1T = 0x1d, BC1T = 0x1d,
@ -16121,10 +16119,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
generate_exception_err(ctx, EXCP_CpU, 1); generate_exception_err(ctx, EXCP_CpU, 1);
} }
break; break;
case BPOSGE64:
case BPOSGE32:
/* MIPS DSP: not implemented */
/* Fall through */
default: default:
MIPS_INVAL("pool32i"); MIPS_INVAL("pool32i");
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);