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target/riscv: Validate the mode in write_vstvec 

Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
Therefore, the encoding of the MODE should also be restricted to 0 and 1.

Signed-off-by: Jiayi Li <lijiayi@eswincomputing.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240701022553.1982-1-lijiayi@eswincomputing.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Jiayi Li 2024-07-01 10:25:53 +08:00 committed by Alistair Francis
parent ae4bdcef6f
commit 910c18a917
1 changed files with 6 additions and 1 deletions
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7
target/riscv/csr.c
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@ -3791,7 +3791,12 @@ static RISCVException read_vstvec(CPURISCVState *env, int csrno,
static RISCVException write_vstvec(CPURISCVState *env, int csrno,
target_ulong val)
{
env->vstvec = val;
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
if ((val & 3) < 2) {
env->vstvec = val;
} else {
qemu_log_mask(LOG_UNIMP, "CSR_VSTVEC: reserved mode not supported\n");
}
return RISCV_EXCP_NONE;
}