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target/arm: Use tcg_constant in 2misc expanders 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-26 09:30:16 -07:00 committed by Peter Maydell
parent d26fc8643e
commit 90e2d33ff9
1 changed files with 10 additions and 30 deletions
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40
target/arm/translate-a64.c
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@ -10089,7 +10089,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
int passes = scalar ? 1 : 2;
if (scalar) {
tcg_res[1] = tcg_const_i32(0);
tcg_res[1] = tcg_constant_i32(0);
}
for (pass = 0; pass < passes; pass++) {
@ -10267,9 +10267,7 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
}
if (is_scalar) {
TCGv_i64 tcg_zero = tcg_const_i64(0);
write_vec_element(s, tcg_zero, rd, 0, MO_64);
tcg_temp_free_i64(tcg_zero);
write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
}
write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
}
@ -10452,23 +10450,17 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
}
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
tcg_fpstatus);
break;
}
default:
g_assert_not_reached();
}
@ -10640,8 +10632,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
if (round) {
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
} else {
tcg_round = NULL;
}
@ -10659,9 +10650,6 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
} else {
write_vec_element(s, tcg_final, rd, 1, MO_64);
}
if (round) {
tcg_temp_free_i64(tcg_round);
}
tcg_temp_free_i64(tcg_rn);
tcg_temp_free_i64(tcg_rd);
tcg_temp_free_i64(tcg_final);
@ -12365,7 +12353,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
}
}
if (!is_q) {
tcg_res[1] = tcg_const_i64(0);
tcg_res[1] = tcg_constant_i64(0);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
@ -12798,25 +12786,17 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x3a: /* FCVTPS */
case 0x3b: /* FCVTZS */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_tosls(tcg_res, tcg_op,
tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
{
TCGv_i32 tcg_shift = tcg_const_i32(0);
gen_helper_vfp_touls(tcg_res, tcg_op,
tcg_shift, tcg_fpstatus);
tcg_temp_free_i32(tcg_shift);
tcg_constant_i32(0), tcg_fpstatus);
break;
}
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */