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hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader 

When writing the secondary-CPU stub boot loader code to the guest,
use arm_write_bootloader() instead of directly calling
rom_add_blob_fixed().  This fixes a bug on big-endian hosts, because
arm_write_bootloader() will correctly byte-swap the host-byte-order
array values into the guest-byte-order to write into the guest
memory.

Cc: qemu-stable@nongnu.org
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230424152717.1333930-3-peter.maydell@linaro.org
[PMM: Moved the "make arm_write_bootloader() function public" part
 to its own patch; updated commit message to note that this fixes
 an actual bug; adjust to the API changes noted in previous commit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2023-04-24 16:27:16 +01:00 committed by Peter Maydell
parent 0fe43f0abf
commit 902bba549f
1 changed files with 20 additions and 18 deletions
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38
hw/arm/aspeed.c
View File

@ -200,33 +200,35 @@ struct AspeedMachineState {
static void aspeed_write_smpboot(ARMCPU *cpu, static void aspeed_write_smpboot(ARMCPU *cpu,
const struct arm_boot_info *info) const struct arm_boot_info *info)
{ {
static const uint32_t poll_mailbox_ready[] = { AddressSpace *as = arm_boot_address_space(cpu, info);
static const ARMInsnFixup poll_mailbox_ready[] = {
/* /*
* r2 = per-cpu go sign value * r2 = per-cpu go sign value
* r1 = AST_SMP_MBOX_FIELD_ENTRY * r1 = AST_SMP_MBOX_FIELD_ENTRY
* r0 = AST_SMP_MBOX_FIELD_GOSIGN * r0 = AST_SMP_MBOX_FIELD_GOSIGN
*/ */
0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
0xe21000ff, /* ands r0, r0, #255 */ { 0xe21000ff }, /* ands r0, r0, #255 */
0xe59f201c, /* ldr r2, [pc, #28] */ { 0xe59f201c }, /* ldr r2, [pc, #28] */
0xe1822000, /* orr r2, r2, r0 */ { 0xe1822000 }, /* orr r2, r2, r0 */
0xe59f1018, /* ldr r1, [pc, #24] */ { 0xe59f1018 }, /* ldr r1, [pc, #24] */
0xe59f0018, /* ldr r0, [pc, #24] */ { 0xe59f0018 }, /* ldr r0, [pc, #24] */
0xe320f002, /* wfe */ { 0xe320f002 }, /* wfe */
0xe5904000, /* ldr r4, [r0] */ { 0xe5904000 }, /* ldr r4, [r0] */
0xe1520004, /* cmp r2, r4 */ { 0xe1520004 }, /* cmp r2, r4 */
0x1afffffb, /* bne <wfe> */ { 0x1afffffb }, /* bne <wfe> */
0xe591f000, /* ldr pc, [r1] */ { 0xe591f000 }, /* ldr pc, [r1] */
AST_SMP_MBOX_GOSIGN, { AST_SMP_MBOX_GOSIGN },
AST_SMP_MBOX_FIELD_ENTRY, { AST_SMP_MBOX_FIELD_ENTRY },
AST_SMP_MBOX_FIELD_GOSIGN, { AST_SMP_MBOX_FIELD_GOSIGN },
{ 0, FIXUP_TERMINATOR }
}; };
static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
sizeof(poll_mailbox_ready), poll_mailbox_ready, fixupcontext);
info->smp_loader_start);
} }
static void aspeed_reset_secondary(ARMCPU *cpu, static void aspeed_reset_secondary(ARMCPU *cpu,