From 9023594b4081585518faf9b144bce62067381990 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Wed, 28 Aug 2019 18:26:31 +0200 Subject: [PATCH] target/mips: Clean up handling of CP0 register 6 Clean up handling of CP0 register 6. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1567009614-12438-8-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/cpu.h | 6 +++++ target/mips/translate.c | 56 ++++++++++++++++++++--------------------- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ed1a97409b..a0c6a6f150 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -321,6 +321,12 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG05__PWSIZE 7 /* CP0 Register 06 */ #define CP0_REG06__WIRED 0 +#define CP0_REG06__SRSCONF0 1 +#define CP0_REG06__SRSCONF1 2 +#define CP0_REG06__SRSCONF2 3 +#define CP0_REG06__SRSCONF3 4 +#define CP0_REG06__SRSCONF4 5 +#define CP0_REG06__PWCTL 6 /* CP0 Register 07 */ #define CP0_REG07__HWRENA 0 /* CP0 Register 08 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 19f86f263a..a914fe4705 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7046,36 +7046,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); register_name = "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name = "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name = "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name = "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name = "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name = "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); register_name = "PWCtl"; @@ -7778,36 +7778,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_helper_mtc0_wired(cpu_env, arg); register_name = "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name = "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name = "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name = "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name = "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name = "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_helper_mtc0_pwctl(cpu_env, arg); register_name = "PWCtl"; @@ -8523,36 +8523,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); register_name = "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name = "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name = "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name = "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name = "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name = "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); register_name = "PWCtl"; @@ -9237,36 +9237,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_helper_mtc0_wired(cpu_env, arg); register_name = "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name = "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name = "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name = "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name = "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name = "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_helper_mtc0_pwctl(cpu_env, arg); register_name = "PWCtl";