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target/riscv: rvv-1.0: floating-point/integer type-convert instructions 

Add the following instructions:

* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v

Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-62-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:47 +08:00 committed by Alistair Francis
parent 986c895de1
commit 900da87ab9
2 changed files with 59 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
target/riscv/insn32.decode
View File

@ -585,10 +585,13 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm

84
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -1,5 +1,4 @@
/* /*
* RISC-V translation routines for the RVV Standard Extension.
* *
* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
* *
@ -2369,34 +2368,41 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
vext_check_ss(s, a->rd, a->rs2, a->vm); vext_check_ss(s, a->rd, a->rs2, a->vm);
} }
#define GEN_OPFV_TRANS(NAME, CHECK) \ static bool do_opfv(DisasContext *s, arg_rmr *a,
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_gvec_3_ptr *fn,
{ \ bool (*checkfn)(DisasContext *, arg_rmr *),
if (CHECK(s, a)) { \ int rm)
uint32_t data = 0; \ {
static gen_helper_gvec_3_ptr * const fns[3] = { \ if (checkfn(s, a)) {
gen_helper_##NAME##_h, \ uint32_t data = 0;
gen_helper_##NAME##_w, \ TCGLabel *over = gen_new_label();
gen_helper_##NAME##_d, \ gen_set_rm(s, rm);
}; \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
\ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
data = FIELD_DP32(data, VDATA, VM, a->vm); \ vreg_ofs(s, a->rs2), cpu_env,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ s->vlen / 8, s->vlen / 8, data, fn);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ mark_vs_dirty(s);
vreg_ofs(s, a->rs2), cpu_env, \ gen_set_label(over);
s->vlen / 8, s->vlen / 8, data, \ return true;
fns[s->sew - 1]); \ }
mark_vs_dirty(s); \ return false;
gen_set_label(over); \
return true; \
} \
return false; \
} }
GEN_OPFV_TRANS(vfsqrt_v, opfv_check) #define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d \
}; \
return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \
}
GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point MIN/MAX Instructions */ /* Vector Floating-Point MIN/MAX Instructions */
GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
@ -2442,7 +2448,7 @@ GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */ /* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check) GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point Merge Instruction */ /* Vector Floating-Point Merge Instruction */
GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
@ -2496,10 +2502,24 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
} }
/* Single-Width Floating-Point/Integer Type-Convert Instructions */ /* Single-Width Floating-Point/Integer Type-Convert Instructions */
GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) #define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) { \
GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
gen_helper_##HELPER##_d \
}; \
return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \
}
GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN)
GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN)
GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN)
GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN)
/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */
GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ)
GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ)
/* Widening Floating-Point/Integer Type-Convert Instructions */ /* Widening Floating-Point/Integer Type-Convert Instructions */