mirror of https://github.com/xemu-project/xemu.git
target/riscv: vector widening integer add and subtract
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-12-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
43740e3a3b
commit
8fcdf77630
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@ -300,3 +300,52 @@ DEF_HELPER_FLAGS_4(vec_rsubs8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(vec_rsubs16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(vec_rsubs32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(vec_rsubs64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_6(vwaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwaddu_wx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsubu_wx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_wx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_wx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwadd_wx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_wx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_wx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwsub_wx_w, void, ptr, ptr, tl, ptr, env, i32)
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@ -286,6 +286,22 @@ vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
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vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
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vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
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vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
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vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
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vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
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vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
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vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
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vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
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vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
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vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
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vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
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vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
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vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
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vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
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vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
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vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
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vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
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vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
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vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -138,6 +138,14 @@ static bool vext_check_nf(DisasContext *s, uint32_t nf)
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return (1 << s->lmul) * nf <= 8;
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}
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/*
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* The destination vector register group cannot overlap a source vector register
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* group of a different element width. (Section 11.2)
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*/
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static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
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{
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return ((rd >= rs + slen) || (rs >= rd + dlen));
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}
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/* common translation macro */
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#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
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@ -1063,3 +1071,181 @@ static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
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}
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GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
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/* Vector Widening Integer Add/Subtract */
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/* OPIVV with WIDEN */
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static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
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1 << s->lmul) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
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gen_helper_gvec_4_ptr *fn,
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bool (*checkfn)(DisasContext *, arg_rmrr *))
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{
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if (checkfn(s, a)) {
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uint32_t data = 0;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1),
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vreg_ofs(s, a->rs2),
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cpu_env, 0, s->vlen / 8,
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data, fn);
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gen_set_label(over);
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return true;
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}
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return false;
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}
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#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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static gen_helper_gvec_4_ptr * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w \
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}; \
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return do_opivv_widen(s, a, fns[s->sew], CHECK); \
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}
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GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
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GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
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GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
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GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
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/* OPIVX with WIDEN */
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static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
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gen_helper_opivx *fn)
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{
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if (opivx_widen_check(s, a)) {
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return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
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}
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return true;
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}
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#define GEN_OPIVX_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w \
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}; \
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return do_opivx_widen(s, a, fns[s->sew]); \
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}
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GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
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GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
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GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
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GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
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/* WIDEN OPIVV with WIDEN */
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static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
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1 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
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gen_helper_gvec_4_ptr *fn)
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{
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if (opiwv_widen_check(s, a)) {
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uint32_t data = 0;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs1),
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vreg_ofs(s, a->rs2),
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cpu_env, 0, s->vlen / 8, data, fn);
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gen_set_label(over);
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return true;
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}
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return false;
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}
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#define GEN_OPIWV_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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static gen_helper_gvec_4_ptr * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w \
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}; \
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return do_opiwv_widen(s, a, fns[s->sew]); \
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}
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GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
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GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
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GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
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GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
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/* WIDEN OPIVX with WIDEN */
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static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, true) &&
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vext_check_reg(s, a->rd, true) &&
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vext_check_reg(s, a->rs2, true) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
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gen_helper_opivx *fn)
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{
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if (opiwx_widen_check(s, a)) {
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return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
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}
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return false;
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}
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#define GEN_OPIWX_WIDEN_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w \
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}; \
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return do_opiwx_widen(s, a, fns[s->sew]); \
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}
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GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
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GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
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GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
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GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
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@ -1017,3 +1017,114 @@ void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc)
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*(uint64_t *)(d + i) = b - *(uint64_t *)(a + i);
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}
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}
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/* Vector Widening Integer Add/Subtract */
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#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
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#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
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#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
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#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
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#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
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#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
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#define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t
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#define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t
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#define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t
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#define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
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#define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
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#define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
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RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD)
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RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD)
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RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD)
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RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB)
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RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB)
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RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
|
||||
RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
|
||||
RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
|
||||
GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq)
|
||||
GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh)
|
||||
GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl)
|
||||
GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq)
|
||||
|
||||
RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
|
||||
RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
|
||||
RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
|
||||
GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq)
|
||||
GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh)
|
||||
GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl)
|
||||
GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
|
||||
|
|
|
|||
Loading…
Reference in New Issue