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target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() 

This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.

riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:49 -03:00 committed by Alistair Francis
parent 7295b18606
commit 8ef67c6637
1 changed files with 1 additions and 2 deletions
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3
target/riscv/cpu.c
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@ -403,11 +403,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_misa(env, MXL_RV64, RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;