mirror of https://github.com/xemu-project/xemu.git
q800: move GLUE device into separate q800-glue.c file
This will allow the q800-glue.h header to be included separately so that the GLUE device can be referenced externally. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230621085353.113233-8-mark.cave-ayland@ilande.co.uk> [lv: update comment] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Mark Cave-Ayland
Laurent Vivier
parent
0b9b41fb8b
commit
8e0932802f
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@ -1225,6 +1225,7 @@ q800
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M: Laurent Vivier <laurent@vivier.eu>
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M: Laurent Vivier <laurent@vivier.eu>
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S: Maintained
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S: Maintained
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F: hw/m68k/q800.c
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F: hw/m68k/q800.c
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F: hw/m68k/q800-glue.c
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F: hw/misc/mac_via.c
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F: hw/misc/mac_via.c
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F: hw/nubus/*
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F: hw/nubus/*
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F: hw/display/macfb.c
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F: hw/display/macfb.c
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@ -1237,6 +1238,7 @@ F: include/hw/nubus/*
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F: include/hw/display/macfb.h
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F: include/hw/display/macfb.h
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F: include/hw/block/swim.h
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F: include/hw/block/swim.h
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F: include/hw/m68k/q800.h
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F: include/hw/m68k/q800.h
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F: include/hw/m68k/q800-glue.h
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virt
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virt
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M: Laurent Vivier <laurent@vivier.eu>
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M: Laurent Vivier <laurent@vivier.eu>
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@ -2,7 +2,7 @@ m68k_ss = ss.source_set()
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m68k_ss.add(when: 'CONFIG_AN5206', if_true: files('an5206.c', 'mcf5206.c'))
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m68k_ss.add(when: 'CONFIG_AN5206', if_true: files('an5206.c', 'mcf5206.c'))
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m68k_ss.add(when: 'CONFIG_MCF5208', if_true: files('mcf5208.c', 'mcf_intc.c'))
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m68k_ss.add(when: 'CONFIG_MCF5208', if_true: files('mcf5208.c', 'mcf_intc.c'))
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m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cube.c'))
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m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cube.c'))
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m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c'))
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m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c', 'q800-glue.c'))
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m68k_ss.add(when: 'CONFIG_M68K_VIRT', if_true: files('virt.c'))
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m68k_ss.add(when: 'CONFIG_M68K_VIRT', if_true: files('virt.c'))
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hw_arch += {'m68k': m68k_ss}
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hw_arch += {'m68k': m68k_ss}
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@ -0,0 +1,252 @@
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/*
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* QEMU q800 logic GLUE (General Logic Unit)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/m68k/q800-glue.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "hw/nmi.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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/*
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* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
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* that performs a variety of functions (RAM management, clock generation, ...).
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* The GLUE chip receives interrupt requests from various devices,
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* assign priority to each, and asserts one or more interrupt line to the
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* CPU.
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*/
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/*
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* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
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* controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
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* in NetBSD as follows:
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*
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* A/UX mode (Linux, NetBSD, auxmode GPIO low)
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*
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* Level 0: Spurious: ignored
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* Level 1: Software
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* Level 2: VIA2 (except ethernet, sound)
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* Level 3: Ethernet
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* Level 4: Serial (SCC)
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* Level 5: Sound
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* Level 6: VIA1
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* Level 7: NMIs: parity errors, RESET button, YANCC error
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*
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* Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
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*
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* Level 0: Spurious: ignored
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* Level 1: VIA1 (clock, ADB)
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* Level 2: VIA2 (NuBus, SCSI)
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* Level 3:
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* Level 4: Serial (SCC)
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* Level 5:
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* Level 6:
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* Level 7: Non-maskable: parity errors, RESET button
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*
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* Note that despite references to A/UX mode in Linux and NetBSD, at least
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* A/UX 3.0.1 still uses Classic mode.
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*/
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static void GLUE_set_irq(void *opaque, int irq, int level)
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{
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GLUEState *s = opaque;
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int i;
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if (s->auxmode) {
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/* Classic mode */
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switch (irq) {
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case GLUE_IRQ_IN_VIA1:
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irq = 0;
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break;
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case GLUE_IRQ_IN_VIA2:
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irq = 1;
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break;
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case GLUE_IRQ_IN_SONIC:
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/* Route to VIA2 instead */
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qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level);
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return;
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case GLUE_IRQ_IN_ESCC:
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irq = 3;
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break;
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case GLUE_IRQ_IN_NMI:
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irq = 6;
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break;
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default:
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g_assert_not_reached();
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}
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} else {
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/* A/UX mode */
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switch (irq) {
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case GLUE_IRQ_IN_VIA1:
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irq = 5;
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break;
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case GLUE_IRQ_IN_VIA2:
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irq = 1;
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break;
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case GLUE_IRQ_IN_SONIC:
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irq = 2;
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break;
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case GLUE_IRQ_IN_ESCC:
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irq = 3;
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break;
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case GLUE_IRQ_IN_NMI:
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irq = 6;
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (level) {
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s->ipr |= 1 << irq;
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} else {
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s->ipr &= ~(1 << irq);
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}
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for (i = 7; i >= 0; i--) {
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if ((s->ipr >> i) & 1) {
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m68k_set_irq_level(s->cpu, i + 1, i + 25);
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return;
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}
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}
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m68k_set_irq_level(s->cpu, 0, 0);
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}
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static void glue_auxmode_set_irq(void *opaque, int irq, int level)
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{
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GLUEState *s = GLUE(opaque);
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s->auxmode = level;
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}
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static void glue_nmi(NMIState *n, int cpu_index, Error **errp)
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{
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GLUEState *s = GLUE(n);
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/* Hold NMI active for 100ms */
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GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1);
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timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
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}
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static void glue_nmi_release(void *opaque)
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{
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GLUEState *s = GLUE(opaque);
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GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
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}
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static void glue_reset(DeviceState *dev)
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{
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GLUEState *s = GLUE(dev);
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s->ipr = 0;
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s->auxmode = 0;
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timer_del(s->nmi_release);
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}
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static const VMStateDescription vmstate_glue = {
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.name = "q800-glue",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(ipr, GLUEState),
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VMSTATE_UINT8(auxmode, GLUEState),
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VMSTATE_TIMER_PTR(nmi_release, GLUEState),
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VMSTATE_END_OF_LIST(),
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},
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};
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/*
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* If the m68k CPU implemented its inbound irq lines as GPIO lines
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* rather than via the m68k_set_irq_level() function we would not need
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* this cpu link property and could instead provide outbound IRQ lines
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* that the board could wire up to the CPU.
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*/
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static Property glue_properties[] = {
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DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void glue_finalize(Object *obj)
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{
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GLUEState *s = GLUE(obj);
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timer_free(s->nmi_release);
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}
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static void glue_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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GLUEState *s = GLUE(dev);
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qdev_init_gpio_in(dev, GLUE_set_irq, 8);
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qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
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qdev_init_gpio_out(dev, s->irqs, 1);
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/* NMI release timer */
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s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
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}
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static void glue_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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NMIClass *nc = NMI_CLASS(klass);
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dc->vmsd = &vmstate_glue;
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dc->reset = glue_reset;
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device_class_set_props(dc, glue_properties);
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nc->nmi_monitor_handler = glue_nmi;
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}
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static const TypeInfo glue_info = {
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.name = TYPE_GLUE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GLUEState),
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.instance_init = glue_init,
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.instance_finalize = glue_finalize,
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.class_init = glue_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_NMI },
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{ }
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},
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};
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static void glue_register_types(void)
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{
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type_register_static(&glue_info);
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}
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type_init(glue_register_types)
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238
hw/m68k/q800.c
238
hw/m68k/q800.c
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@ -28,7 +28,6 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/boards.h"
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#include "hw/or-irq.h"
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#include "hw/or-irq.h"
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#include "hw/nmi.h"
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#include "elf.h"
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#include "elf.h"
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#include "hw/loader.h"
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#include "hw/loader.h"
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#include "ui/console.h"
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#include "ui/console.h"
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@ -39,6 +38,7 @@
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#include "standard-headers/asm-m68k/bootinfo-mac.h"
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#include "standard-headers/asm-m68k/bootinfo-mac.h"
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#include "bootinfo.h"
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#include "bootinfo.h"
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#include "hw/m68k/q800.h"
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#include "hw/m68k/q800.h"
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#include "hw/m68k/q800-glue.h"
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#include "hw/misc/mac_via.h"
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#include "hw/misc/mac_via.h"
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#include "hw/input/adb.h"
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#include "hw/input/adb.h"
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#include "hw/nubus/mac-nubus-bridge.h"
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#include "hw/nubus/mac-nubus-bridge.h"
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@ -88,241 +88,6 @@
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#define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
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#define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
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BIT(0xe))
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BIT(0xe))
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/*
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* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
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* that performs a variety of functions (RAM management, clock generation, ...).
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* The GLUE chip receives interrupt requests from various devices,
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* assign priority to each, and asserts one or more interrupt line to the
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* CPU.
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*/
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#define TYPE_GLUE "q800-glue"
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OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE)
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struct GLUEState {
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SysBusDevice parent_obj;
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M68kCPU *cpu;
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uint8_t ipr;
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uint8_t auxmode;
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qemu_irq irqs[1];
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QEMUTimer *nmi_release;
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};
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#define GLUE_IRQ_IN_VIA1 0
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#define GLUE_IRQ_IN_VIA2 1
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#define GLUE_IRQ_IN_SONIC 2
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#define GLUE_IRQ_IN_ESCC 3
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#define GLUE_IRQ_IN_NMI 4
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#define GLUE_IRQ_NUBUS_9 0
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/*
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* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
|
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* controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
|
|
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* in NetBSD as follows:
|
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*
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* A/UX mode (Linux, NetBSD, auxmode GPIO low)
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*
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* Level 0: Spurious: ignored
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* Level 1: Software
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* Level 2: VIA2 (except ethernet, sound)
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* Level 3: Ethernet
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* Level 4: Serial (SCC)
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* Level 5: Sound
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* Level 6: VIA1
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* Level 7: NMIs: parity errors, RESET button, YANCC error
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*
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* Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
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*
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* Level 0: Spurious: ignored
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|
||||||
* Level 1: VIA1 (clock, ADB)
|
|
||||||
* Level 2: VIA2 (NuBus, SCSI)
|
|
||||||
* Level 3:
|
|
||||||
* Level 4: Serial (SCC)
|
|
||||||
* Level 5:
|
|
||||||
* Level 6:
|
|
||||||
* Level 7: Non-maskable: parity errors, RESET button
|
|
||||||
*
|
|
||||||
* Note that despite references to A/UX mode in Linux and NetBSD, at least
|
|
||||||
* A/UX 3.0.1 still uses Classic mode.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static void GLUE_set_irq(void *opaque, int irq, int level)
|
|
||||||
{
|
|
||||||
GLUEState *s = opaque;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (s->auxmode) {
|
|
||||||
/* Classic mode */
|
|
||||||
switch (irq) {
|
|
||||||
case GLUE_IRQ_IN_VIA1:
|
|
||||||
irq = 0;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_VIA2:
|
|
||||||
irq = 1;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_SONIC:
|
|
||||||
/* Route to VIA2 instead */
|
|
||||||
qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level);
|
|
||||||
return;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_ESCC:
|
|
||||||
irq = 3;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_NMI:
|
|
||||||
irq = 6;
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
g_assert_not_reached();
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
/* A/UX mode */
|
|
||||||
switch (irq) {
|
|
||||||
case GLUE_IRQ_IN_VIA1:
|
|
||||||
irq = 5;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_VIA2:
|
|
||||||
irq = 1;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_SONIC:
|
|
||||||
irq = 2;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_ESCC:
|
|
||||||
irq = 3;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case GLUE_IRQ_IN_NMI:
|
|
||||||
irq = 6;
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
g_assert_not_reached();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (level) {
|
|
||||||
s->ipr |= 1 << irq;
|
|
||||||
} else {
|
|
||||||
s->ipr &= ~(1 << irq);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 7; i >= 0; i--) {
|
|
||||||
if ((s->ipr >> i) & 1) {
|
|
||||||
m68k_set_irq_level(s->cpu, i + 1, i + 25);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
m68k_set_irq_level(s->cpu, 0, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_auxmode_set_irq(void *opaque, int irq, int level)
|
|
||||||
{
|
|
||||||
GLUEState *s = GLUE(opaque);
|
|
||||||
|
|
||||||
s->auxmode = level;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_nmi(NMIState *n, int cpu_index, Error **errp)
|
|
||||||
{
|
|
||||||
GLUEState *s = GLUE(n);
|
|
||||||
|
|
||||||
/* Hold NMI active for 100ms */
|
|
||||||
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1);
|
|
||||||
timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_nmi_release(void *opaque)
|
|
||||||
{
|
|
||||||
GLUEState *s = GLUE(opaque);
|
|
||||||
|
|
||||||
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_reset(DeviceState *dev)
|
|
||||||
{
|
|
||||||
GLUEState *s = GLUE(dev);
|
|
||||||
|
|
||||||
s->ipr = 0;
|
|
||||||
s->auxmode = 0;
|
|
||||||
|
|
||||||
timer_del(s->nmi_release);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const VMStateDescription vmstate_glue = {
|
|
||||||
.name = "q800-glue",
|
|
||||||
.version_id = 0,
|
|
||||||
.minimum_version_id = 0,
|
|
||||||
.fields = (VMStateField[]) {
|
|
||||||
VMSTATE_UINT8(ipr, GLUEState),
|
|
||||||
VMSTATE_UINT8(auxmode, GLUEState),
|
|
||||||
VMSTATE_TIMER_PTR(nmi_release, GLUEState),
|
|
||||||
VMSTATE_END_OF_LIST(),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If the m68k CPU implemented its inbound irq lines as GPIO lines
|
|
||||||
* rather than via the m68k_set_irq_level() function we would not need
|
|
||||||
* this cpu link property and could instead provide outbound IRQ lines
|
|
||||||
* that the board could wire up to the CPU.
|
|
||||||
*/
|
|
||||||
static Property glue_properties[] = {
|
|
||||||
DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *),
|
|
||||||
DEFINE_PROP_END_OF_LIST(),
|
|
||||||
};
|
|
||||||
|
|
||||||
static void glue_finalize(Object *obj)
|
|
||||||
{
|
|
||||||
GLUEState *s = GLUE(obj);
|
|
||||||
|
|
||||||
timer_free(s->nmi_release);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_init(Object *obj)
|
|
||||||
{
|
|
||||||
DeviceState *dev = DEVICE(obj);
|
|
||||||
GLUEState *s = GLUE(dev);
|
|
||||||
|
|
||||||
qdev_init_gpio_in(dev, GLUE_set_irq, 8);
|
|
||||||
qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
|
|
||||||
|
|
||||||
qdev_init_gpio_out(dev, s->irqs, 1);
|
|
||||||
|
|
||||||
/* NMI release timer */
|
|
||||||
s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void glue_class_init(ObjectClass *klass, void *data)
|
|
||||||
{
|
|
||||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
||||||
NMIClass *nc = NMI_CLASS(klass);
|
|
||||||
|
|
||||||
dc->vmsd = &vmstate_glue;
|
|
||||||
dc->reset = glue_reset;
|
|
||||||
device_class_set_props(dc, glue_properties);
|
|
||||||
nc->nmi_monitor_handler = glue_nmi;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const TypeInfo glue_info = {
|
|
||||||
.name = TYPE_GLUE,
|
|
||||||
.parent = TYPE_SYS_BUS_DEVICE,
|
|
||||||
.instance_size = sizeof(GLUEState),
|
|
||||||
.instance_init = glue_init,
|
|
||||||
.instance_finalize = glue_finalize,
|
|
||||||
.class_init = glue_class_init,
|
|
||||||
.interfaces = (InterfaceInfo[]) {
|
|
||||||
{ TYPE_NMI },
|
|
||||||
{ }
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static void main_cpu_reset(void *opaque)
|
static void main_cpu_reset(void *opaque)
|
||||||
{
|
{
|
||||||
|
|
@ -763,7 +528,6 @@ static const TypeInfo q800_machine_typeinfo = {
|
||||||
static void q800_machine_register_types(void)
|
static void q800_machine_register_types(void)
|
||||||
{
|
{
|
||||||
type_register_static(&q800_machine_typeinfo);
|
type_register_static(&q800_machine_typeinfo);
|
||||||
type_register_static(&glue_info);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
type_init(q800_machine_register_types)
|
type_init(q800_machine_register_types)
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* QEMU q800 logic GLUE (General Logic Unit)
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HW_Q800_GLUE_H
|
||||||
|
#define HW_Q800_GLUE_H
|
||||||
|
|
||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "hw/sysbus.h"
|
||||||
|
|
||||||
|
#define TYPE_GLUE "q800-glue"
|
||||||
|
OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE)
|
||||||
|
|
||||||
|
struct GLUEState {
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
|
||||||
|
M68kCPU *cpu;
|
||||||
|
uint8_t ipr;
|
||||||
|
uint8_t auxmode;
|
||||||
|
qemu_irq irqs[1];
|
||||||
|
QEMUTimer *nmi_release;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define GLUE_IRQ_IN_VIA1 0
|
||||||
|
#define GLUE_IRQ_IN_VIA2 1
|
||||||
|
#define GLUE_IRQ_IN_SONIC 2
|
||||||
|
#define GLUE_IRQ_IN_ESCC 3
|
||||||
|
#define GLUE_IRQ_IN_NMI 4
|
||||||
|
|
||||||
|
#define GLUE_IRQ_NUBUS_9 0
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue