mirror of https://github.com/xemu-project/xemu.git
target/ppc: Fix SPE unavailable exception triggering
When emulating certain floating point instructions or vector instructions on PowerPC machines, QEMU did not properly generate the SPE/Embedded Floating- Point Unavailable interrupt. See the buglink further below for references to the relevant NXP documentation. This patch fixes the behavior of some evfs* instructions that were incorrectly emitting the interrupt. More importantly, this patch fixes the behavior of several efd* and ev* instructions that were not generating the interrupt. Triggering the interrupt for these instructions fixes lazy FPU/vector context switching on some operating systems like Linux. Without this patch, the result of some double-precision arithmetic could be corrupted due to the lack of proper saving and restoring of the upper 32-bit part of the general-purpose registers. Buglink: https://bugs.launchpad.net/qemu/+bug/1888918 Buglink: https://bugs.launchpad.net/qemu/+bug/1611394 Signed-off-by: Matthieu Bucchianeri <matthieu.bucchianeri@leostella.com> Message-Id: <20200727175553.32276-1-matthieu.bucchianeri@leostella.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Matthieu Bucchianeri
David Gibson
parent
c4b8b49d68
commit
8dcdb535d7
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@ -349,14 +349,24 @@ static inline void gen_evmergelohi(DisasContext *ctx)
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}
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static inline void gen_evsplati(DisasContext *ctx)
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{
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uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
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uint64_t imm;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
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tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
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tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
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}
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static inline void gen_evsplatfi(DisasContext *ctx)
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{
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uint64_t imm = rA(ctx->opcode) << 27;
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uint64_t imm;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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imm = rA(ctx->opcode) << 27;
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tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
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tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
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@ -389,21 +399,37 @@ static inline void gen_evsel(DisasContext *ctx)
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static void gen_evsel0(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel1(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel2(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel3(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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@ -518,6 +544,11 @@ static inline void gen_evmwsmia(DisasContext *ctx)
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{
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TCGv_i64 tmp;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evmwsmi(ctx); /* rD := rA * rB */
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tmp = tcg_temp_new_i64();
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@ -534,6 +565,11 @@ static inline void gen_evmwsmiaa(DisasContext *ctx)
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TCGv_i64 acc;
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TCGv_i64 tmp;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evmwsmi(ctx); /* rD := rA * rB */
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acc = tcg_temp_new_i64();
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@ -892,8 +928,14 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_32_64(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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TCGv_i64 t0; \
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TCGv_i32 t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i32(); \
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gen_load_gpr64(t0, rB(ctx->opcode)); \
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gen_helper_##name(t1, cpu_env, t0); \
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tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
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@ -903,8 +945,14 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_64_32(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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TCGv_i64 t0; \
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TCGv_i32 t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i32(); \
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
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gen_helper_##name(t0, cpu_env, t1); \
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gen_store_gpr64(rD(ctx->opcode), t0); \
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@ -914,7 +962,12 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_64_64(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i64 t0; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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gen_load_gpr64(t0, rB(ctx->opcode)); \
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gen_helper_##name(t0, cpu_env, t0); \
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gen_store_gpr64(rD(ctx->opcode), t0); \
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@ -923,13 +976,8 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_ARITH2_32_32(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i32 t0, t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i32(); \
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t1 = tcg_temp_new_i32(); \
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TCGv_i32 t0 = tcg_temp_new_i32(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
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gen_helper_##name(t0, cpu_env, t0, t1); \
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@ -958,13 +1006,8 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_COMP_32(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i32 t0, t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i32(); \
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t1 = tcg_temp_new_i32(); \
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TCGv_i32 t0 = tcg_temp_new_i32(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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\
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
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@ -1074,28 +1117,16 @@ GEN_SPEFPUOP_ARITH2_32_32(efsmul);
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GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
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static inline void gen_efsabs(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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(target_long)~0x80000000LL);
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}
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static inline void gen_efsnabs(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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0x80000000);
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}
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static inline void gen_efsneg(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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0x80000000);
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}
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