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target/sh4: Fix code style for checkpatch.pl 

We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210127232151.3523581-2-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-27 23:53:21 +01:00
parent 91e92cad67
commit 8d2b06fbc2
1 changed files with 41 additions and 41 deletions
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22
target/sh4/helper.c
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@ -371,8 +371,8 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
if (n >= 0) { if (n >= 0) {
matching = &env->utlb[n]; matching = &env->utlb[n];
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE : n = (rw == 1)
MMU_DTLB_VIOLATION_READ; ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
} else if ((rw == 1) && !(matching->pr & 1)) { } else if ((rw == 1) && !(matching->pr & 1)) {
n = MMU_DTLB_VIOLATION_WRITE; n = MMU_DTLB_VIOLATION_WRITE;
} else if ((rw == 1) && !matching->d) { } else if ((rw == 1) && !matching->d) {
@ -384,14 +384,14 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
} }
} }
} else if (n == MMU_DTLB_MISS) { } else if (n == MMU_DTLB_MISS) {
n = (rw == 1) ? MMU_DTLB_MISS_WRITE : n = (rw == 1)
MMU_DTLB_MISS_READ; ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
} }
} }
if (n >= 0) { if (n >= 0) {
n = MMU_OK; n = MMU_OK;
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) | *physical = ((matching->ppn << 10) & ~(matching->size - 1))
(address & (matching->size - 1)); | (address & (matching->size - 1));
} }
return n; return n;
} }
@ -401,19 +401,19 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int rw, int access_type) int rw, int access_type)
{ {
/* P1, P2 and P4 areas do not use translation */ /* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) || if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
address >= 0xe0000000) {
if (!(env->sr & (1u << SR_MD)) if (!(env->sr & (1u << SR_MD))
&& (address < 0xe0000000 || address >= 0xe4000000)) { && (address < 0xe0000000 || address >= 0xe4000000)) {
/* Unauthorized access in user mode (only store queues are available) */ /* Unauthorized access in user mode (only store queues are available) */
qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n"); qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
if (rw == 0) if (rw == 0) {
return MMU_DADDR_ERROR_READ; return MMU_DADDR_ERROR_READ;
else if (rw == 1) } else if (rw == 1) {
return MMU_DADDR_ERROR_WRITE; return MMU_DADDR_ERROR_WRITE;
else } else {
return MMU_IADDR_ERROR; return MMU_IADDR_ERROR;
} }
}
if (address >= 0x80000000 && address < 0xc0000000) { if (address >= 0x80000000 && address < 0xc0000000) {
/* Mask upper 3 bits for P1 and P2 areas */ /* Mask upper 3 bits for P1 and P2 areas */
*physical = address & 0x1fffffff; *physical = address & 0x1fffffff;