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target/arm: mark the 32bit alias of PAR when LPAE enabled 

We also mark it ARM_CP_NO_GDB so we avoid duplicate PAR's in the
system register XML we send to gdb.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231107105145.2916124-1-alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée 2023-11-06 18:50:53 +00:00
parent 940bb5fa9c
commit 8ce4d441cb
1 changed files with 21 additions and 14 deletions
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35
target/arm/helper.c
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@ -3722,20 +3722,6 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
} }
#endif #endif
static const ARMCPRegInfo vapa_cp_reginfo[] = {
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .resetvalue = 0,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write },
#ifndef CONFIG_USER_ONLY
/* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
.writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
#endif
};
/* Return basic MPU access permission bits. */ /* Return basic MPU access permission bits. */
static uint32_t simple_mpu_ap_bits(uint32_t val) static uint32_t simple_mpu_ap_bits(uint32_t val)
{ {
@ -8904,6 +8890,27 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, generic_timer_cp_reginfo); define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
} }
if (arm_feature(env, ARM_FEATURE_VAPA)) { if (arm_feature(env, ARM_FEATURE_VAPA)) {
ARMCPRegInfo vapa_cp_reginfo[] = {
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .resetvalue = 0,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write},
#ifndef CONFIG_USER_ONLY
/* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
.writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
#endif
};
/*
* When LPAE exists this 32-bit PAR register is an alias of the
* 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
*/
if (arm_feature(env, ARM_FEATURE_LPAE)) {
vapa_cp_reginfo[0].type = ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
define_arm_cp_regs(cpu, vapa_cp_reginfo); define_arm_cp_regs(cpu, vapa_cp_reginfo);
} }
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {