mirror of https://github.com/xemu-project/xemu.git
hw/nvme fixes
- use the stl/ldl pci dma api -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmTGuc8ACgkQTeGvMW1P Dek41wgAwqgRmtUhmmaQJJpF5Pya3J7n3Zkbp+cULdnSp/su7W7yIUTcTzdbr34d 9LbNHmWerXYinlIxG08ZWw2lq0TwApKj+8gv/wf8H7dG86/pBYfoQvOlkNx2QKyR vtRNlILCEbJpbSfY3LbFNvRGOkArr6HkzT4hZprUIfCvRg58u5oIxEx/ZYa+m3WU ED0y/46e7HbVbmbwJKrn4EK3k0zGdFyeINRZ5TB5DML3lCTX6eaZTLUXGIb7LLcK Xyv6/TCkPTggDszTam24kx0A7DhC+3f2C8DsJg7H8jnWb1F+oq/2EJam/0HU22Uk n348MrWOusuF7kbHMCP9h28gYT3aWw== =KjVO -----END PGP SIGNATURE----- Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into staging hw/nvme fixes - use the stl/ldl pci dma api # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmTGuc8ACgkQTeGvMW1P # Dek41wgAwqgRmtUhmmaQJJpF5Pya3J7n3Zkbp+cULdnSp/su7W7yIUTcTzdbr34d # 9LbNHmWerXYinlIxG08ZWw2lq0TwApKj+8gv/wf8H7dG86/pBYfoQvOlkNx2QKyR # vtRNlILCEbJpbSfY3LbFNvRGOkArr6HkzT4hZprUIfCvRg58u5oIxEx/ZYa+m3WU # ED0y/46e7HbVbmbwJKrn4EK3k0zGdFyeINRZ5TB5DML3lCTX6eaZTLUXGIb7LLcK # Xyv6/TCkPTggDszTam24kx0A7DhC+3f2C8DsJg7H8jnWb1F+oq/2EJam/0HU22Uk # n348MrWOusuF7kbHMCP9h28gYT3aWw== # =KjVO # -----END PGP SIGNATURE----- # gpg: Signature made Sun 30 Jul 2023 12:28:15 PM PDT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu: hw/nvme: use stl/ldl pci dma api Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
8cb945be2d
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@ -1468,20 +1468,16 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset,
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static void nvme_update_cq_eventidx(const NvmeCQueue *cq)
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{
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uint32_t v = cpu_to_le32(cq->head);
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trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head);
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pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v));
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stl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->ei_addr, cq->head,
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MEMTXATTRS_UNSPECIFIED);
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}
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static void nvme_update_cq_head(NvmeCQueue *cq)
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{
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uint32_t v;
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pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &v, sizeof(v));
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cq->head = le32_to_cpu(v);
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ldl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head,
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MEMTXATTRS_UNSPECIFIED);
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trace_pci_nvme_update_cq_head(cq->cqid, cq->head);
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}
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@ -6801,7 +6797,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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PCIDevice *pci = PCI_DEVICE(n);
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uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1);
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uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2);
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uint32_t v;
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int i;
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/* Address should be page aligned */
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@ -6819,8 +6814,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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NvmeCQueue *cq = n->cq[i];
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if (sq) {
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v = cpu_to_le32(sq->tail);
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/*
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* CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3)
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* nvme_process_db() uses this hard-coded way to calculate
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@ -6828,7 +6821,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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*/
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sq->db_addr = dbs_addr + (i << 3);
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sq->ei_addr = eis_addr + (i << 3);
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pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail));
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stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED);
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if (n->params.ioeventfd && sq->sqid != 0) {
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if (!nvme_init_sq_ioeventfd(sq)) {
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@ -6838,12 +6831,10 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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}
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if (cq) {
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v = cpu_to_le32(cq->head);
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/* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */
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cq->db_addr = dbs_addr + (i << 3) + (1 << 2);
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cq->ei_addr = eis_addr + (i << 3) + (1 << 2);
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pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head));
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stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED);
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if (n->params.ioeventfd && cq->cqid != 0) {
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if (!nvme_init_cq_ioeventfd(cq)) {
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@ -6974,20 +6965,16 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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static void nvme_update_sq_eventidx(const NvmeSQueue *sq)
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{
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uint32_t v = cpu_to_le32(sq->tail);
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trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail);
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pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &v, sizeof(v));
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stl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->ei_addr, sq->tail,
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MEMTXATTRS_UNSPECIFIED);
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}
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static void nvme_update_sq_tail(NvmeSQueue *sq)
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{
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uint32_t v;
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pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &v, sizeof(v));
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sq->tail = le32_to_cpu(v);
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ldl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail,
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MEMTXATTRS_UNSPECIFIED);
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trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail);
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}
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@ -7592,7 +7579,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
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static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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{
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PCIDevice *pci = PCI_DEVICE(n);
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uint32_t qid, v;
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uint32_t qid;
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if (unlikely(addr & ((1 << 2) - 1))) {
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NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
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@ -7659,8 +7646,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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start_sqs = nvme_cq_full(cq) ? 1 : 0;
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cq->head = new_head;
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if (!qid && n->dbbuf_enabled) {
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v = cpu_to_le32(cq->head);
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pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head));
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stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED);
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}
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if (start_sqs) {
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NvmeSQueue *sq;
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@ -7720,8 +7706,6 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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sq->tail = new_tail;
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if (!qid && n->dbbuf_enabled) {
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v = cpu_to_le32(sq->tail);
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/*
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* The spec states "the host shall also update the controller's
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* corresponding doorbell property to match the value of that entry
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@ -7735,7 +7719,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
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* including ones that run on Linux, are not updating Admin Queues,
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* so we can't trust reading it for an appropriate sq tail.
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*/
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pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail));
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stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED);
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}
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qemu_bh_schedule(sq->bh);
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